JP2024531904A - 経時変化の緩和 - Google Patents

経時変化の緩和 Download PDF

Info

Publication number
JP2024531904A
JP2024531904A JP2024505580A JP2024505580A JP2024531904A JP 2024531904 A JP2024531904 A JP 2024531904A JP 2024505580 A JP2024505580 A JP 2024505580A JP 2024505580 A JP2024505580 A JP 2024505580A JP 2024531904 A JP2024531904 A JP 2024531904A
Authority
JP
Japan
Prior art keywords
input
signal
signal path
output
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024505580A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024531904A5 (https=
Inventor
ナラシマン、ムクンド
アデ、ムラリ・クリシュナ
アルール・ディラビヤム、アルン・デイビッド
グプタ、マヤンク
アンドレーエフ、ボリス・ディミトロフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2024531904A publication Critical patent/JP2024531904A/ja
Publication of JP2024531904A5 publication Critical patent/JP2024531904A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2024505580A 2021-08-06 2022-07-06 経時変化の緩和 Pending JP2024531904A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/396,046 2021-08-06
US17/396,046 US11971741B2 (en) 2021-08-06 2021-08-06 Aging mitigation
PCT/US2022/036199 WO2023014460A1 (en) 2021-08-06 2022-07-06 Aging mitigation

Publications (2)

Publication Number Publication Date
JP2024531904A true JP2024531904A (ja) 2024-09-03
JP2024531904A5 JP2024531904A5 (https=) 2025-06-17

Family

ID=82748577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024505580A Pending JP2024531904A (ja) 2021-08-06 2022-07-06 経時変化の緩和

Country Status (8)

Country Link
US (1) US11971741B2 (https=)
EP (1) EP4381603A1 (https=)
JP (1) JP2024531904A (https=)
KR (1) KR20240039133A (https=)
CN (1) CN117769805A (https=)
PH (1) PH12023553288A1 (https=)
TW (1) TW202308319A (https=)
WO (1) WO2023014460A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11881862B2 (en) * 2021-08-17 2024-01-23 Qualcomm Incorporated Mitigation of duty-cycle distortion
US11967358B2 (en) * 2022-05-26 2024-04-23 Micron Technology, Inc. Apparatuses and methods for bias temperature instability mitigation
US20240235545A9 (en) * 2022-10-23 2024-07-11 Intel Corporation Adaptive clock gating for improving wear out-induced duty cycle shift in computer clock network

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU762154A1 (ru) * 1978-11-28 1980-09-07 Aleksandr M Botov Устройство определения временного положения основного максимума периодического сигнала 1
US5583461A (en) * 1994-09-19 1996-12-10 Advanced Micro Devices, Inc. Internal clock signal generation circuit having external clock detection and a selectable internal clock pulse
JPH09252252A (ja) * 1996-03-14 1997-09-22 Sanyo Electric Co Ltd Ｄ／ａ変換器
US5694056A (en) * 1996-04-01 1997-12-02 Xilinx, Inc. Fast pipeline frame full detector
US6275478B1 (en) * 1998-07-10 2001-08-14 Qualcomm Incorporated Methods and apparatuses for fast power control of signals transmitted on a multiple access channel
US6657979B1 (en) * 1999-08-23 2003-12-02 Motorola, Inc. Reduced power consumption multiplexer using self-decoding power down logic
JP3923715B2 (ja) * 2000-09-29 2007-06-06 株式会社東芝 メモリカード
US6864726B2 (en) * 2003-06-17 2005-03-08 Intel Corporation Output signal control from a DAC-driven amplifier-based driver
KR101136036B1 (ko) * 2003-12-24 2012-04-18 삼성전자주식회사 유휴 모드에서의 전력 소모가 감소된 프로세서 시스템 및그 방법
JP2005208259A (ja) * 2004-01-21 2005-08-04 Optrex Corp 有機ｅｌディスプレイ装置の駆動装置および駆動方法
US7760749B2 (en) * 2007-01-11 2010-07-20 Via Technologies, Inc. Apparatus and method for deskewing 1000 BASE-T Ethernet physical layer signals
DE102007006385B4 (de) * 2007-02-08 2019-02-14 Infineon Technologies Ag Eine Schaltkreis-Anordnung, ein Prozessor mit einer Schaltkreis-Anordnung, ein elektrisches Gerät und ein Verfahren zum Betreiben einer Schaltkreis-Anordnung
US7839194B2 (en) * 2007-11-21 2010-11-23 Rambus Inc. Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
JP2012222497A (ja) * 2011-04-06 2012-11-12 Renesas Electronics Corp 受信回路及びエラー検出方法
KR101851614B1 (ko) * 2011-12-12 2018-06-12 삼성전자주식회사 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템
JP2014093682A (ja) * 2012-11-05 2014-05-19 Denso Corp 通信システム
JP6032082B2 (ja) * 2013-03-25 2016-11-24 富士通株式会社 受信回路及び半導体集積回路
US9071235B2 (en) * 2013-10-18 2015-06-30 Micron Technology, Inc. Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port
US9401223B2 (en) * 2014-05-09 2016-07-26 Oracle International Corporation At-speed test of memory arrays using scan
US9966960B2 (en) * 2014-12-17 2018-05-08 Silicon Laboratories Inc. Configurable logic circuit including dynamic lookup table
CN104639042B (zh) * 2014-12-24 2017-11-17 聚辰半导体(上海)有限公司 低功耗可调倍频器
US9606604B1 (en) * 2015-11-25 2017-03-28 Globalfoundries Inc. Energy efficient high-speed link and method to maximize energy savings on the energy efficient high-speed link
JP6639348B2 (ja) * 2016-07-20 2020-02-05 シナプティクス・ジャパン合同会社 表示制御デバイス及び表示パネルモジュール
US10110229B1 (en) * 2017-06-06 2018-10-23 Intel Corporation Aging-resistant signal path circuitry
US10878879B2 (en) * 2017-06-21 2020-12-29 Mediatek Inc. Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window
TWI739269B (zh) * 2020-01-08 2021-09-11 瑞昱半導體股份有限公司 適應信號輸入模態的信號接收裝置及其信號處理方法

Also Published As

Publication number Publication date
TW202308319A (zh) 2023-02-16
WO2023014460A1 (en) 2023-02-09
US20230038670A1 (en) 2023-02-09
CN117769805A (zh) 2024-03-26
EP4381603A1 (en) 2024-06-12
PH12023553288A1 (en) 2024-03-18
US11971741B2 (en) 2024-04-30
KR20240039133A (ko) 2024-03-26

Similar Documents

Publication Publication Date Title
US12314113B2 (en) Memory controller operable in data loop-back mode
US6812799B2 (en) Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
CN109643566B (zh) 用于调整命令信号路径的延迟的设备及方法
JP2024531904A (ja) 経時変化の緩和
US8427892B2 (en) Write strobe generation for a memory interface controller
US20190244655A1 (en) Memory device parallelizer
US20100052739A1 (en) Device and control method of device
US7292500B2 (en) Reducing read data strobe latency in a memory system
KR100883140B1 (ko) 데이터 출력 제어회로, 반도체 메모리 장치 및 그의 동작방법
US10984850B2 (en) Apparatuses and methods for switching refresh state in a memory circuit
US20080030249A1 (en) Measure control delay and method having latching circuit integral with delay circuit
US7178048B2 (en) System and method for signal synchronization based on plural clock signals
US8176352B2 (en) Clock domain data transfer device and methods thereof
WO2008048835A1 (en) Read-data stage circuitry for ddr-sdram memory controller
US7392406B2 (en) Circuit and method for generating clock signals for clocking digital signal processor and memory
US7876641B2 (en) Semiconductor integrated circuit
KR100968444B1 (ko) 데이터 출력 인에이블 신호 생성 회로 및 그를 구비하는반도체 메모리 장치
JP4425243B2 (ja) 半導体記憶装置
US20070091691A1 (en) Wide window clock scheme for loading output FIFO registers
US6982573B2 (en) Switchable clock source
US7786814B2 (en) Method and apparatus for deriving an integrated circuit (IC) clock with a frequency offset from an IC system clock
KR100853465B1 (ko) 내부리드신호 생성회로와 이를 포함하는 반도체 메모리장치
JP2001057078A (ja) パケットコマンド駆動型メモリ素子のロード信号発生回路
JP2000163173A (ja) 出力同時動作低減回路
KR20080003993A (ko) 어드레스 플립플롭 회로 및 제어방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250606