PH12023553288A1 - Aging mitigation - Google Patents

Aging mitigation

Info

Publication number
PH12023553288A1
PH12023553288A1 PH1/2023/553288A PH12023553288A PH12023553288A1 PH 12023553288 A1 PH12023553288 A1 PH 12023553288A1 PH 12023553288 A PH12023553288 A PH 12023553288A PH 12023553288 A1 PH12023553288 A1 PH 12023553288A1
Authority
PH
Philippines
Prior art keywords
aging
signal path
input
low
transistors
Prior art date
Application number
PH1/2023/553288A
Other languages
English (en)
Inventor
Murali Krishna Ade
Boris Dimitrov Andreev
Diraviyam Arun David Arul
Mayank Gupta
Mukund Narasimhan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of PH12023553288A1 publication Critical patent/PH12023553288A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
PH1/2023/553288A 2021-08-06 2022-07-06 Aging mitigation PH12023553288A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/396,046 US11971741B2 (en) 2021-08-06 2021-08-06 Aging mitigation
PCT/US2022/036199 WO2023014460A1 (en) 2021-08-06 2022-07-06 Aging mitigation

Publications (1)

Publication Number Publication Date
PH12023553288A1 true PH12023553288A1 (en) 2024-03-18

Family

ID=82748577

Family Applications (1)

Application Number Title Priority Date Filing Date
PH1/2023/553288A PH12023553288A1 (en) 2021-08-06 2022-07-06 Aging mitigation

Country Status (8)

Country Link
US (1) US11971741B2 (https=)
EP (1) EP4381603A1 (https=)
JP (1) JP2024531904A (https=)
KR (1) KR20240039133A (https=)
CN (1) CN117769805A (https=)
PH (1) PH12023553288A1 (https=)
TW (1) TW202308319A (https=)
WO (1) WO2023014460A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11881862B2 (en) * 2021-08-17 2024-01-23 Qualcomm Incorporated Mitigation of duty-cycle distortion
US11967358B2 (en) * 2022-05-26 2024-04-23 Micron Technology, Inc. Apparatuses and methods for bias temperature instability mitigation
US20240235545A9 (en) * 2022-10-23 2024-07-11 Intel Corporation Adaptive clock gating for improving wear out-induced duty cycle shift in computer clock network

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US5694056A (en) * 1996-04-01 1997-12-02 Xilinx, Inc. Fast pipeline frame full detector
US6275478B1 (en) * 1998-07-10 2001-08-14 Qualcomm Incorporated Methods and apparatuses for fast power control of signals transmitted on a multiple access channel
US6657979B1 (en) * 1999-08-23 2003-12-02 Motorola, Inc. Reduced power consumption multiplexer using self-decoding power down logic
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KR101136036B1 (ko) * 2003-12-24 2012-04-18 삼성전자주식회사 유휴 모드에서의 전력 소모가 감소된 프로세서 시스템 및그 방법
JP2005208259A (ja) * 2004-01-21 2005-08-04 Optrex Corp 有機ｅｌディスプレイ装置の駆動装置および駆動方法
US7760749B2 (en) * 2007-01-11 2010-07-20 Via Technologies, Inc. Apparatus and method for deskewing 1000 BASE-T Ethernet physical layer signals
DE102007006385B4 (de) * 2007-02-08 2019-02-14 Infineon Technologies Ag Eine Schaltkreis-Anordnung, ein Prozessor mit einer Schaltkreis-Anordnung, ein elektrisches Gerät und ein Verfahren zum Betreiben einer Schaltkreis-Anordnung
US7839194B2 (en) * 2007-11-21 2010-11-23 Rambus Inc. Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
JP2012222497A (ja) * 2011-04-06 2012-11-12 Renesas Electronics Corp 受信回路及びエラー検出方法
KR101851614B1 (ko) * 2011-12-12 2018-06-12 삼성전자주식회사 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템
JP2014093682A (ja) * 2012-11-05 2014-05-19 Denso Corp 通信システム
JP6032082B2 (ja) * 2013-03-25 2016-11-24 富士通株式会社 受信回路及び半導体集積回路
US9071235B2 (en) * 2013-10-18 2015-06-30 Micron Technology, Inc. Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power
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US9966960B2 (en) * 2014-12-17 2018-05-08 Silicon Laboratories Inc. Configurable logic circuit including dynamic lookup table
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US9606604B1 (en) * 2015-11-25 2017-03-28 Globalfoundries Inc. Energy efficient high-speed link and method to maximize energy savings on the energy efficient high-speed link
JP6639348B2 (ja) * 2016-07-20 2020-02-05 シナプティクス・ジャパン合同会社 表示制御デバイス及び表示パネルモジュール
US10110229B1 (en) * 2017-06-06 2018-10-23 Intel Corporation Aging-resistant signal path circuitry
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Also Published As

Publication number Publication date
TW202308319A (zh) 2023-02-16
WO2023014460A1 (en) 2023-02-09
US20230038670A1 (en) 2023-02-09
JP2024531904A (ja) 2024-09-03
CN117769805A (zh) 2024-03-26
EP4381603A1 (en) 2024-06-12
US11971741B2 (en) 2024-04-30
KR20240039133A (ko) 2024-03-26

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