JP2024531580A5 - - Google Patents

Info

Publication number
JP2024531580A5
JP2024531580A5 JP2024514544A JP2024514544A JP2024531580A5 JP 2024531580 A5 JP2024531580 A5 JP 2024531580A5 JP 2024514544 A JP2024514544 A JP 2024514544A JP 2024514544 A JP2024514544 A JP 2024514544A JP 2024531580 A5 JP2024531580 A5 JP 2024531580A5
Authority
JP
Japan
Prior art keywords
board
substrate
metal layer
package
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024514544A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024531580A (ja
Filing date
Publication date
Priority claimed from US17/482,294 external-priority patent/US12100649B2/en
Application filed filed Critical
Publication of JP2024531580A publication Critical patent/JP2024531580A/ja
Publication of JP2024531580A5 publication Critical patent/JP2024531580A5/ja
Pending legal-status Critical Current

Links

JP2024514544A 2021-09-22 2022-08-23 背面金属層を有する集積デバイスを備えるパッケージ Pending JP2024531580A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/482,294 US12100649B2 (en) 2021-09-22 2021-09-22 Package comprising an integrated device with a back side metal layer
US17/482,294 2021-09-22
PCT/US2022/041235 WO2023048882A1 (en) 2021-09-22 2022-08-23 Package comprising an integrated device with a back side metal layer

Publications (2)

Publication Number Publication Date
JP2024531580A JP2024531580A (ja) 2024-08-29
JP2024531580A5 true JP2024531580A5 (enExample) 2025-08-19

Family

ID=83283303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024514544A Pending JP2024531580A (ja) 2021-09-22 2022-08-23 背面金属層を有する集積デバイスを備えるパッケージ

Country Status (7)

Country Link
US (1) US12100649B2 (enExample)
EP (1) EP4406025A1 (enExample)
JP (1) JP2024531580A (enExample)
KR (1) KR20240058871A (enExample)
CN (1) CN117941065A (enExample)
TW (1) TW202329367A (enExample)
WO (1) WO2023048882A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230245985A1 (en) * 2022-02-01 2023-08-03 Skyworks Solutions, Inc. Shielded wafer level chip scale package with shield connected to ground via redistribution layers
US20250385153A1 (en) * 2024-06-12 2025-12-18 Avago Technologies International Sales Pte. Limited Thermal management systems and methods for semiconductor devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8461676B2 (en) * 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
CN104471707B (zh) * 2012-07-26 2017-07-04 株式会社村田制作所 半导体模块
DE102015101440B4 (de) * 2015-02-02 2021-05-06 Infineon Technologies Ag Halbleiterbauelement mit unter dem Package angeordnetem Chip und Verfahren zur Montage desselben auf einer Anwendungsplatine
US10453802B2 (en) * 2017-08-30 2019-10-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure, semiconductor device and method for manufacturing the same
US10332862B2 (en) 2017-09-07 2019-06-25 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10937741B2 (en) * 2018-11-16 2021-03-02 STATS ChipPAC Pte. Ltd. Molded laser package with electromagnetic interference shield and method of making
KR102632367B1 (ko) * 2018-12-04 2024-02-02 삼성전기주식회사 반도체 패키지
US20210175178A1 (en) * 2019-12-05 2021-06-10 Qualcomm Incorporated Package comprising a double-sided redistribution portion
US20210280507A1 (en) * 2020-03-05 2021-09-09 Qualcomm Incorporated Package comprising dummy interconnects
US11551939B2 (en) * 2020-09-02 2023-01-10 Qualcomm Incorporated Substrate comprising interconnects embedded in a solder resist layer

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