JP2024507541A - チップセンサのためのオープンパッケージ - Google Patents

チップセンサのためのオープンパッケージ Download PDF

Info

Publication number
JP2024507541A
JP2024507541A JP2023550606A JP2023550606A JP2024507541A JP 2024507541 A JP2024507541 A JP 2024507541A JP 2023550606 A JP2023550606 A JP 2023550606A JP 2023550606 A JP2023550606 A JP 2023550606A JP 2024507541 A JP2024507541 A JP 2024507541A
Authority
JP
Japan
Prior art keywords
interconnect substrate
die
aperture
interconnect
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023550606A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024507541A5 (https=
Inventor
ゲオルグ ミュルナー アーネスト
リューデルス マイケル
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by テキサス インスツルメンツ インコーポレイテッド filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2024507541A publication Critical patent/JP2024507541A/ja
Publication of JP2024507541A5 publication Critical patent/JP2024507541A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/479—Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H10W74/017—Auxiliary layers for moulds, e.g. release layers or layers preventing residue
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
JP2023550606A 2021-02-23 2022-02-18 チップセンサのためのオープンパッケージ Pending JP2024507541A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163152375P 2021-02-23 2021-02-23
US63/152,375 2021-02-23
US17/363,200 2021-06-30
US17/363,200 US20220270960A1 (en) 2021-02-23 2021-06-30 Open-Cavity Package for Chip Sensor
PCT/US2022/016891 WO2022182575A1 (en) 2021-02-23 2022-02-18 Open-cavity package for chip sensor

Publications (2)

Publication Number Publication Date
JP2024507541A true JP2024507541A (ja) 2024-02-20
JP2024507541A5 JP2024507541A5 (https=) 2025-01-31

Family

ID=82899862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023550606A Pending JP2024507541A (ja) 2021-02-23 2022-02-18 チップセンサのためのオープンパッケージ

Country Status (5)

Country Link
US (1) US20220270960A1 (https=)
EP (1) EP4298404A4 (https=)
JP (1) JP2024507541A (https=)
CN (1) CN116940807A (https=)
WO (1) WO2022182575A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230183880A1 (en) * 2021-12-15 2023-06-15 Texas Instruments Incorporated Fluid sensor package

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050046044A1 (en) * 2002-02-07 2005-03-03 Horst Theuss Semiconductor device with sensor and/or actuator surface and method for producing it
JP2013516329A (ja) * 2009-12-31 2013-05-13 日本テキサス・インスツルメンツ株式会社 マイクロ・エレクトロ・メカニカル・システム（ＭＥＭＳ）デバイスのための音響（ａｃｏｕｓｔｉｃ）エアチャネルを有するリードフレームベースのプリモールドされたパッケージ
JP2015517919A (ja) * 2012-02-27 2015-06-25 日本テキサス・インスツルメンツ株式会社 制御されたキャビティｍｅｍｓパッケージを集積化ボードに埋め込むための方法
JP2016151427A (ja) * 2015-02-16 2016-08-22 ローム株式会社 電子装置
US20200075565A1 (en) * 2018-08-29 2020-03-05 Phoenix & Corporation Package structure for semiconductor device and manufacturing method thereof
EP3640978A1 (en) * 2018-10-15 2020-04-22 IMEC vzw A method for packaging semiconductor dies
US20200279797A1 (en) * 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Flex-foil package with coplanar topology for high-frequency signals

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6982491B1 (en) * 2004-01-20 2006-01-03 Asat Ltd. Sensor semiconductor package and method of manufacturing the same
US7495325B2 (en) * 2005-05-05 2009-02-24 Stats Chippac, Ltd. Optical die-down quad flat non-leaded package
US20080191333A1 (en) * 2007-02-08 2008-08-14 Advanced Chip Engineering Technology Inc. Image sensor package with die receiving opening and method of the same
US7582954B1 (en) * 2008-02-25 2009-09-01 National Semiconductor Corporation Optical leadless leadframe package
US8907457B2 (en) * 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US10121043B2 (en) * 2014-11-18 2018-11-06 Sunasic Technologies, Inc. Printed circuit board assembly with image sensor mounted thereon
US9663357B2 (en) * 2015-07-15 2017-05-30 Texas Instruments Incorporated Open cavity package using chip-embedding technology
DE102015116081A1 (de) * 2015-09-23 2017-03-23 Infineon Technologies Ag Elektronisches Sensorbauelement mit einem Flip-Chip-montierten Halbleiterchip und einem Substrat mit einer Öffnung
TWI698968B (zh) * 2016-07-04 2020-07-11 大陸商蘇州晶方半導體科技股份有限公司 封裝結構以及封裝方法
EP3396329A1 (en) * 2017-04-28 2018-10-31 Sensirion AG Sensor package
JP7110888B2 (ja) * 2018-10-03 2022-08-02 Tdk株式会社 センサー用パッケージ基板及びこれを備えるセンサーモジュール
CN113207244B (zh) * 2020-02-03 2024-12-10 奥特斯奥地利科技与系统技术有限公司 制造部件承载件的方法及部件承载件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050046044A1 (en) * 2002-02-07 2005-03-03 Horst Theuss Semiconductor device with sensor and/or actuator surface and method for producing it
JP2013516329A (ja) * 2009-12-31 2013-05-13 日本テキサス・インスツルメンツ株式会社 マイクロ・エレクトロ・メカニカル・システム（ＭＥＭＳ）デバイスのための音響（ａｃｏｕｓｔｉｃ）エアチャネルを有するリードフレームベースのプリモールドされたパッケージ
JP2015517919A (ja) * 2012-02-27 2015-06-25 日本テキサス・インスツルメンツ株式会社 制御されたキャビティｍｅｍｓパッケージを集積化ボードに埋め込むための方法
JP2016151427A (ja) * 2015-02-16 2016-08-22 ローム株式会社 電子装置
US20200075565A1 (en) * 2018-08-29 2020-03-05 Phoenix & Corporation Package structure for semiconductor device and manufacturing method thereof
EP3640978A1 (en) * 2018-10-15 2020-04-22 IMEC vzw A method for packaging semiconductor dies
US20200279797A1 (en) * 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Flex-foil package with coplanar topology for high-frequency signals

Also Published As

Publication number Publication date
US20220270960A1 (en) 2022-08-25
CN116940807A (zh) 2023-10-24
WO2022182575A1 (en) 2022-09-01
EP4298404A4 (en) 2024-09-11
EP4298404A1 (en) 2024-01-03

Similar Documents

Publication Publication Date Title
CN100385641C (zh) 具有局部预制图形化引线框架的半导体封装及其制造方法
CN101546718B (zh) 半导体装置封装和制造半导体装置封装的方法
JP3155741B2 (ja) Ｃｓｐのｂｇａ構造を備えた半導体パッケージ
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
KR20050055782A (ko) 이미지 센서 장치
US20050184404A1 (en) Photosensitive semiconductor package with support member and method for fabricating the same
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
CN112670252A (zh) 具有分离的衬底区段的封装体
KR20190068468A (ko) 공기 캐비티를 갖는 반도체 패키지
JP2002110718A (ja) 半導体装置の製造方法
US11139233B2 (en) Cavity wall structure for semiconductor packaging
TW202226464A (zh) 具有堆疊被動組件的多層半導體封裝
KR100826393B1 (ko) 전도성 패턴을 갖는 실링 라인으로 구비된 웨이퍼 레벨디바이스 패키지 및 그 패키징 방법
KR20060042872A (ko) 반도체장치의 실장 방법
KR101674537B1 (ko) 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지
CN206301777U (zh) 半导体封装件
US8415793B2 (en) Wafer and substructure for use in manufacturing electronic component packages
JP2024507541A (ja) チップセンサのためのオープンパッケージ
KR20010001159A (ko) 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
KR100829613B1 (ko) 반도체 칩 패키지 및 그 제조 방법
CN215731589U (zh) 无带引线框封装件和集成电路封装件
CN102412224A (zh) 用于半导体封装的连接芯片焊盘的引线框架
CN100466209C (zh) 半导体器件及其加工和封装方法
US10622270B2 (en) Integrated circuit package with stress directing material
KR100390453B1 (ko) 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250123

A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20250123

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20260130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20260218