JP2023110900A - ナノラミネート絶縁ゲート構造を有するワイドバンドギャップトランジスタ及びワイドバンドギャップトランジスタの製造方法 - Google Patents
ナノラミネート絶縁ゲート構造を有するワイドバンドギャップトランジスタ及びワイドバンドギャップトランジスタの製造方法 Download PDFInfo
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- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01332—Making the insulator
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- H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
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- H10D64/01366—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the semiconductor being silicon carbide
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- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102022000001478 | 2022-01-28 | ||
| IT102022000001478A IT202200001478A1 (it) | 2022-01-28 | 2022-01-28 | Transistore ad ampia banda proibita con struttura isolante di porta nanolaminata e procedimento per fabbricare un transistore ad ampia banda proibita |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2023110900A true JP2023110900A (ja) | 2023-08-09 |
| JP2023110900A5 JP2023110900A5 (https=) | 2026-01-20 |
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ID=80933659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023010393A Pending JP2023110900A (ja) | 2022-01-28 | 2023-01-26 | ナノラミネート絶縁ゲート構造を有するワイドバンドギャップトランジスタ及びワイドバンドギャップトランジスタの製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20230246086A1 (https=) |
| EP (1) | EP4220734B1 (https=) |
| JP (1) | JP2023110900A (https=) |
| IT (1) | IT202200001478A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2026009769A1 (ja) * | 2024-07-04 | 2026-01-08 | 東京エレクトロン株式会社 | 成膜方法、成膜装置及び半導体デバイス |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117995661B (zh) * | 2024-01-23 | 2025-02-07 | 安徽大学 | 基于SiC衬底的开关器件栅氧层的制备方法及开关器件 |
-
2022
- 2022-01-28 IT IT102022000001478A patent/IT202200001478A1/it unknown
-
2023
- 2023-01-18 US US18/156,120 patent/US20230246086A1/en active Pending
- 2023-01-19 EP EP23152421.6A patent/EP4220734B1/en active Active
- 2023-01-26 JP JP2023010393A patent/JP2023110900A/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2026009769A1 (ja) * | 2024-07-04 | 2026-01-08 | 東京エレクトロン株式会社 | 成膜方法、成膜装置及び半導体デバイス |
Also Published As
| Publication number | Publication date |
|---|---|
| EP4220734B1 (en) | 2024-11-20 |
| EP4220734A1 (en) | 2023-08-02 |
| US20230246086A1 (en) | 2023-08-03 |
| EP4220734C0 (en) | 2024-11-20 |
| IT202200001478A1 (it) | 2023-07-28 |
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