JP2022551842A - 欠陥低減のためのスクライブレーンパターンを有する集積回路 - Google Patents

欠陥低減のためのスクライブレーンパターンを有する集積回路 Download PDF

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Publication number
JP2022551842A
JP2022551842A JP2022520670A JP2022520670A JP2022551842A JP 2022551842 A JP2022551842 A JP 2022551842A JP 2022520670 A JP2022520670 A JP 2022520670A JP 2022520670 A JP2022520670 A JP 2022520670A JP 2022551842 A JP2022551842 A JP 2022551842A
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JP
Japan
Prior art keywords
scribe lane
wafer
mask
pattern
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022520670A
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English (en)
Japanese (ja)
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JP2022551842A5 (https=
Inventor
サリナス アドリアン
キース マクドナルド ウィリアム
アレクサンダー ヨハネスメイヤ スコット
ポール ルッキン ロバート
アルロン メイスナー ステファン
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
日本テキサス・インスツルメンツ合同会社
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Publication date
Application filed by テキサス インスツルメンツ インコーポレイテッド, 日本テキサス・インスツルメンツ合同会社 filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2022551842A publication Critical patent/JP2022551842A/ja
Publication of JP2022551842A5 publication Critical patent/JP2022551842A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70125—Use of illumination settings tailored to particular mask patterns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
JP2022520670A 2019-10-04 2020-10-05 欠陥低減のためのスクライブレーンパターンを有する集積回路 Pending JP2022551842A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201962910857P 2019-10-04 2019-10-04
US62/910,857 2019-10-04
US16/679,997 US11094644B2 (en) 2019-10-04 2019-11-11 Integrated circuit with scribe lane patterns for defect reduction
US16/679,997 2019-11-11
PCT/US2020/054204 WO2021067909A1 (en) 2019-10-04 2020-10-05 Integrated circuit with scribe lane patterns for defect reduction

Publications (2)

Publication Number Publication Date
JP2022551842A true JP2022551842A (ja) 2022-12-14
JP2022551842A5 JP2022551842A5 (https=) 2023-10-12

Family

ID=75274998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022520670A Pending JP2022551842A (ja) 2019-10-04 2020-10-05 欠陥低減のためのスクライブレーンパターンを有する集積回路

Country Status (5)

Country Link
US (2) US11094644B2 (https=)
EP (1) EP4042474A4 (https=)
JP (1) JP2022551842A (https=)
CN (1) CN114600231A (https=)
WO (1) WO2021067909A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102846584B1 (ko) * 2020-09-09 2025-08-18 삼성전자주식회사 반도체 패키지
GB2644158A (en) * 2024-08-27 2026-03-25 Pragmatic Semiconductor Ltd Integrated circuit chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332556A (ja) * 2000-05-25 2001-11-30 Hitachi Ltd 半導体装置の製造方法
JP2010114130A (ja) * 2008-11-04 2010-05-20 Panasonic Corp 半導体装置及びその製造方法
JP2011061236A (ja) * 2010-11-26 2011-03-24 Renesas Electronics Corp 半導体装置
JP2013222100A (ja) * 2012-04-17 2013-10-28 Fujitsu Semiconductor Ltd レチクル、露光方法、半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2292637B (en) * 1994-08-24 1998-07-22 Nec Corp Semiconductor device
US6068954A (en) * 1998-09-01 2000-05-30 Micron Technology, Inc. Semiconductor wafer alignment methods
US6908830B2 (en) 2003-06-23 2005-06-21 International Business Machines Corporation Method for printing marks on the edges of wafers
US8368180B2 (en) 2009-02-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line metal structure
CN102156392A (zh) * 2010-02-11 2011-08-17 中芯国际集成电路制造(上海)有限公司 光刻机对准参数的检测装置及其检测方法
CN103091971B (zh) * 2011-10-27 2014-07-23 中芯国际集成电路制造(北京)有限公司 掩模板及其制造方法、以及监测掩模板雾状污染的方法
JP2015106693A (ja) * 2013-12-02 2015-06-08 旭化成エレクトロニクス株式会社 半導体ウェハ及び半導体装置の製造方法
CN105336711B (zh) * 2014-06-19 2019-03-15 恩智浦美国有限公司 采用低k值介电材料的管芯边缘密封
JP2017134292A (ja) 2016-01-28 2017-08-03 三重富士通セミコンダクター株式会社 半導体装置の製造方法及びマスクの形成方法
FR3075773B1 (fr) * 2017-12-22 2020-01-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation de dispositifs semi-conducteurs et de chemins de decoupe
WO2020164002A1 (en) * 2019-02-13 2020-08-20 Yangtze Memory Technologies Co., Ltd. Marks for locating patterns in semiconductor fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332556A (ja) * 2000-05-25 2001-11-30 Hitachi Ltd 半導体装置の製造方法
JP2010114130A (ja) * 2008-11-04 2010-05-20 Panasonic Corp 半導体装置及びその製造方法
JP2011061236A (ja) * 2010-11-26 2011-03-24 Renesas Electronics Corp 半導体装置
JP2013222100A (ja) * 2012-04-17 2013-10-28 Fujitsu Semiconductor Ltd レチクル、露光方法、半導体装置の製造方法

Also Published As

Publication number Publication date
EP4042474A1 (en) 2022-08-17
US20210398910A1 (en) 2021-12-23
US11094644B2 (en) 2021-08-17
US20210104468A1 (en) 2021-04-08
WO2021067909A1 (en) 2021-04-08
CN114600231A (zh) 2022-06-07
EP4042474A4 (en) 2022-12-14

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