JP2022067972A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 238000005468 ion implantation Methods 0.000 claims description 105
- 239000012535 impurity Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000009826 distribution Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 7
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- 229910052796 boron Inorganic materials 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
以下の説明において、n型およびp型は半導体の導電型を示し、本開示においては、第1導電型をn型、第2導電型をp型として説明するが、第1導電型をp型、第2導電型をn型としてもよい。
<A-1.構成・動作>
図1に半導体装置100の平面図を、図2に半導体装置100の図1のA-A線における断面図を示す。
半導体装置100では、隣り合うアクティブトレンチ6に挟まれたメサ領域において、エミッタ層4は、隣り合うアクティブトレンチ6のうちの一方のアクティブトレンチ6に接し他方のアクティブトレンチ6には接さないように第1方向に離散的に配置された領域と、他方のアクティブトレンチ6に接し一方のアクティブトレンチ6には接さないように第1方向に離散的に配置された領域と、を有する。また、隣り合うアクティブトレンチ6に挟まれたメサ領域において、コンタクト層5は、平面視で、一方のアクティブトレンチ6に接する側のエミッタ層4と他方のアクティブトレンチ6に接する側のエミッタ層4との間と、第1方向に離散的なエミッタ層4の各領域の間と、に配置されている、これにより、半導体装置100はラッチアップの抑制に適した半導体装置である。
図3にIGBTである半導体装置101の平面図を、図4に半導体装置101の図3のB-B線における断面図を示す。
図5にIGBTである半導体装置102の平面図を、図6に半導体装置102の図5のC-C線における断面図を示す。
図7及び図8にIGBTである半導体装置103の平面図を示す。半導体装置103の構成は、エミッタ層4の第1方向の配置が、第2方向の位置によって異なっていることを除けば、実施の形態1の半導体装置100と同様である。
図9及び図10にIGBTである半導体装置104の平面図を示す。
図11にIGBTである半導体装置105の断面図を示す。
図12にIGBTである半導体装置106の断面図を示す。
図13に半導体装置107の断面図を示す。
図14に半導体装置108の断面図を示す。
図15は実施の形態10の半導体装置の製造方法のフローチャートを示す。本実施の形態では主に実施の形態1の半導体装置100を製造する場合を想定して説明するが、他の実施の形態の半導体装置101から半導体装置108のいずれかを製造する製造方法に対しても同様に適用可能である。
図22は実施の形態11の半導体装置の製造方法のフローチャートを示す。本実施の形態では主に実施の形態1の半導体装置100を製造する場合を想定して説明するが、他の実施の形態の半導体装置101から半導体装置108のいずれかを製造する製造方法に対しても同様に適用可能である。
Claims (22)
- 第1主面および前記第1主面とは逆側の主面である第2主面を有する半導体基体を備え、
前記半導体基体の第1の素子領域にトランジスタが設けられており、
前記半導体基体は、前記第1の素子領域において、
第1導電型の第1半導体層と、
前記第1半導体層よりも前記第1主面側に設けられた第2導電型の第2半導体層と、
前記第2半導体層の前記第1主面側に選択的に設けられた第1導電型の第3半導体層と、
前記第3半導体層と電気的に接続された第1電極と、
前記第2半導体層よりも第2導電型の不純物濃度が高く前記第2半導体層と前記第1電極の間に配置された第4半導体層と、
を備え、
前記半導体基体は、前記第1の素子領域において、前記第1主面から前記第3半導体層及び前記第2半導体層を貫通して前記第1半導体層に到達する複数の第1のトレンチが設けられており、
前記複数の第1のトレンチは平面視でそれぞれ第1方向に延在し、
前記複数の第1のトレンチは平面視でストライプ状に配置されており、
前記複数の第1のトレンチのうちの少なくとも一部は当該第1のトレンチ内にゲート絶縁膜を介して前記第2半導体層と対向するようにゲート電極が設けられたアクティブトレンチであり、
前記複数の第1のトレンチの前記ストライプ状の配置は前記アクティブトレンチが隣り合う部分を有し、
隣り合うトレンチに挟まれた領域であるメサ領域のうち、隣り合う前記アクティブトレンチに挟まれたメサ領域において、前記第3半導体層は、前記隣り合う前記アクティブトレンチのうちの一方の前記アクティブトレンチに接し他方の前記アクティブトレンチには接さないように前記第1方向に離散的に配置された領域と、前記他方のアクティブトレンチに接し前記一方のアクティブトレンチには接さないように前記第1方向に離散的に配置された領域と、を有し、
前記隣り合う前記アクティブトレンチに挟まれた前記メサ領域において、前記第4半導体層は、平面視で、前記一方の前記アクティブトレンチに接する側の前記第3半導体層と前記他方の前記アクティブトレンチに接する側の前記第3半導体層との間と、前記第1方向に離散的な前記第3半導体層の各領域の間と、に配置されている、
半導体装置。 - 請求項1に記載の半導体装置であって、
前記隣り合う前記アクティブトレンチに挟まれた前記メサ領域において、
前記アクティブトレンチの側壁において前記第3半導体層の離散的な領域の1つが接している前記第1方向の幅が、当該前記アクティブトレンチの側壁において前記第1方向に隣接する前記第3半導体層の離散的な領域間の前記第1方向の幅よりも大きい、
半導体装置。 - 請求項1または2に記載の半導体装置であって、
前記隣り合う前記アクティブトレンチに挟まれた前記メサ領域において、前記第4半導体層は、前記隣り合う前記アクティブトレンチの両方に接する連続的な領域であって、前記第1方向の位置に関して前記第3半導体層の前記第1方向に離散的な領域の複数が含まれる連続的な領域、を有する、
半導体装置。 - 請求項1から3のいずれか1項に記載の半導体装置であって、
前記複数の第1のトレンチのうちの一部は当該トレンチ内にゲート絶縁膜を介して形成されたダミーゲート電極を備えるダミートレンチであり、
前記ダミーゲート電極は前記第1電極と電気的に接続されており、
前記第3半導体層はダミートレンチの側壁に接しないように形成されている、
半導体装置。 - 請求項4に記載の半導体装置であって、
前記アクティブトレンチと前記ダミートレンチに挟まれたメサ領域において、前記第3半導体層は、前記アクティブトレンチに接し前記ダミートレンチには接しないように前記第1方向に離散的に配置された領域を有する、
半導体装置。 - 請求項4または5に記載の半導体装置であって、
前記複数の第1のトレンチの前記ストライプ状の配置は前記ダミートレンチが隣り合う部分を有し、
前記半導体基体と前記第1電極の間に、平面視で前記複数の第1のトレンチの前記ストライプ状の配置において隣り合う前記ダミートレンチの間にまたがるように、層間絶縁膜が形成されている、
半導体装置。 - 請求項6に記載の半導体装置であって、
前記半導体基体と前記第1電極の間に、平面視で前記複数の第1のトレンチの前記ストライプ状の配置において隣り合う前記ダミートレンチの間の全体に、前記層間絶縁膜が形成されている、
半導体装置。 - 請求項1から7のいずれか1項に記載の半導体装置であって、
前記第3半導体層の前記第1方向の配置が、第2方向の位置によって異なる、
半導体装置。 - 請求項8に記載の半導体装置であって、
前記第3半導体層の前記第1方向の配置が、前記隣り合う前記アクティブトレンチに挟まれた前記メサ領域において、一方の前記アクティブトレンチ側と他方の前記アクティブトレンチ側で異なる、
半導体装置。 - 請求項8に記載の半導体装置であって、
前記第3半導体層の前記第1方向の配置が、前記アクティブトレンチの両側で異なる、
半導体装置。 - 請求項1から10のいずれか1項に記載の半導体装置であって、
前記第3半導体層の前記第1方向に離散的な前記領域は、第1方向とは垂直な第2方向の幅が第1方向の部分的な領域で広くなっている領域を含む、
半導体装置。 - 請求項1から11のいずれか1項に記載の半導体装置であって、
前記第1の素子領域において前記半導体基体の前記第1主面から前記第2主面側に向けて第2のトレンチが設けられており、
前記第3半導体層は前記第2のトレンチの側壁に露出しており、
前記第4半導体層は前記第2のトレンチの底部に設けられた部分を含み、
前記第1電極は前記第2のトレンチに設けられた部分を含み、
前記第2のトレンチの側面において前記第3半導体層と前記第1電極が接触しており、
前記第2のトレンチの底面において前記第4半導体層と前記第1電極が接触している、
半導体装置。 - 請求項1から11のいずれか1項に記載の半導体装置であって、
前記第4半導体層は、第2半導体層の前記第1主面側に選択的に設けられている、
半導体装置。 - 請求項1から13のいずれか1項に記載の半導体装置であって、
前記第1の素子領域は前記第1半導体層より前記第2主面側に第2導電型の第5半導体層と、
前記第5半導体層と電気的に接続された第2電極と、
を備え、
前記半導体基体の平面視で前記第1の素子領域とは別の第2の素子領域にダイオードが設けられており、
前記第2の素子領域は、
前記第1半導体層と、
前記第1半導体層より第1主面側に配置された第2導電型の第6半導体層と、
前記第1主面から前記第6半導体層を貫通して前記第1半導体層に到達する複数の第3のトレンチと、
前記第3のトレンチ内にゲート絶縁膜を介して配置されたダイオードトレンチ電極と、
前記第1半導体層より第2主面側に配置された第1導電型の第7半導体層と、
前記第7半導体層と電気的に接続された前記第2電極と、
を備え、
前記ダイオードトレンチ電極は前記第1電極と電気的に接続されている、
半導体装置。 - 請求項14に記載の半導体装置であって、
前記第1の素子領域と前記第2の素子領域の間に境界領域を有し、
前記境界領域は、
前記第1半導体層と、
前記第1半導体層より第2主面側に配置された前記第5半導体層と、
前記第1半導体層より第1主面側に配置された前記第6半導体層と、
を備える、
半導体装置。 - 請求項1から15のいずれか1項に記載の半導体装置であって、
前記第4半導体層と前記第3半導体層それぞれの不純物濃度の厚さ方向の分布は1つのピークのみを有する、
半導体装置。 - 請求項1から16のいずれか1項に記載の半導体装置であって、
前記半導体基体は前記第1の素子領域において前記第1半導体層と前記第2半導体層の間に、第1導電型の不純物濃度が前記第1半導体層より高い第8半導体層が設けられている、
半導体装置。 - 請求項17に記載の半導体装置であって、
前記アクティブトレンチ内にはゲート絶縁膜を介して前記ゲート電極とシールド電極とが配置されており、
前記シールド電極は前記第1電極と電気的に接続され、
前記シールド電極の深さ方向の中心は前記ゲート電極の深さ方向の中心より前記第2主面側に位置しており、
前記ゲート電極の前記第2主面側の端は深さ方向において前記第8半導体層が設けられている範囲に含まれている、
半導体装置。 - 請求項1から16のいずれか1項に記載の半導体装置を製造する半導体装置の製造方法であって、
前記第2半導体層を第1イオン注入を通して形成し、
前記第3半導体層を第2イオン注入を通して形成し、
前記第4半導体層を第3イオン注入を通して形成し、
前記第1イオン注入で用いるマスクと、前記第2イオン注入で用いるマスクと、前記第3イオン注入で用いるマスクと、はそれぞれ異なる、
半導体装置の製造方法。 - 請求項17または18に記載の半導体装置を製造する半導体装置の製造方法であって、
前記第2半導体層を第1イオン注入を通して形成し、
前記第3半導体層を第2イオン注入を通して形成し、
前記第4半導体層を第3イオン注入を通して形成し、
前記第8半導体層を第4イオン注入を通して形成し、
前記第1イオン注入と前記第4イオン注入で同じマスクを用い、
前記第1イオン注入および前記第4イオン注入で用いる前記マスクと、前記第2イオン注入で用いるマスクと、前記第3イオン注入で用いるマスクと、はそれぞれ異なる、
半導体装置の製造方法。 - 請求項1から16のいずれか1項に記載の半導体装置を製造する半導体装置の製造方法であって、
前記第2半導体層を第5イオン注入を通して形成し、
前記第3半導体層を第6イオン注入を通して形成し、
前記第4半導体層を第7イオン注入を通して形成し、
前記第5イオン注入と前記第6イオン注入で同じマスクを用い、
前記第5イオン注入と前記第6イオン注入を行った後に、前記第5イオン注入と前記第6イオン注入で用いる前記マスクとは別のマスクを用いて前記第7イオン注入を行う、
半導体装置の製造方法。 - 請求項17または18に記載の半導体装置を製造する半導体装置の製造方法であって、
前記第2半導体層を第5イオン注入を通して形成し、
前記第3半導体層を第6イオン注入を通して形成し、
前記第4半導体層を第7イオン注入を通して形成し、
前記第8半導体層を第8イオン注入を通して形成し、
前記第5イオン注入と前記第6イオン注入と前記第8イオン注入で同じマスクを用い、
前記第5イオン注入と前記第6イオン注入と前記第8イオン注入を行った後に、前記第5イオン注入と前記第6イオン注入と前記第8イオン注入で用いる前記マスクとは別のマスクを用いて前記第7イオン注入を行う、
半導体装置の製造方法。
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