JP2022042635A - 半導体記憶装置 - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4066—Pseudo-SRAMs
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Abstract
Description
図2は、本発明の第1実施形態に係る半導体記憶装置の構成例を示すブロック図である。半導体記憶装置は、制御部10と、メモリ20と、を備える。制御部10及びメモリ20の各々は、専用のハードウェアデバイスや論理回路によって構成されてもよい。
以下、本発明の第2実施形態について説明する。本実施形態の半導体記憶装置は、半導体記憶装置の温度に応じてリフレッシュ間隔を制御する点において、第1実施形態と異なっている。以下、第1実施形態と異なる構成について説明する。
以下、本発明の第3実施形態について説明する。本実施形態の半導体記憶装置は、メモリ20に対する読み出し又は書き込みアクセスが要求された場合に、温度センサによって検出された温度に対応する間隔のうち最短の間隔のリフレッシュトリガ信号がセレクタ150から出力されるように制御する点において、上記各実施形態と異なっている。以下、上記各実施形態と異なる構成について説明する。
20…メモリ
130…セレクタ
140…回路部
150…セレクタ
160…温度センサ
SEL…制御信号
I1…第1間隔
I2…第2間隔
OSC1…第1間隔のリフレッシュトリガ信号
OSC2…第2間隔のリフレッシュトリガ信号
Claims (7)
- メモリのリフレッシュ動作を複数の間隔のうち何れかの間隔で行うように制御する制御部であって、前記メモリに対する読み出し又は書き込みアクセスが要求された場合に、所定の条件を満たすまで前記メモリのリフレッシュ動作を前記複数の間隔のうち最短の間隔で行うように制御する制御部を備える、
半導体記憶装置。 - 前記所定の条件は、前記最短の間隔で前記メモリのリフレッシュ動作が所定回数行われることである、請求項1に記載の半導体記憶装置。
- 前記制御部は、
制御信号に基づいて、前記複数の間隔のうち何れかの間隔のリフレッシュトリガ信号を出力するセレクタと、
前記メモリに対する読み出し又は書き込みアクセスが要求された場合に、前記所定の条件を満たすまで前記最短の間隔のリフレッシュトリガ信号が前記セレクタから出力されるように、前記制御信号を生成して前記セレクタに出力する回路部と、を備える、請求項1又は2に記載の半導体記憶装置。 - 前記半導体記憶装置の温度を検出する温度センサを備え、
前記制御部は、前記半導体記憶装置の温度に対して前記複数の間隔のうち何れかの間隔が対応付けられている場合に、前記複数の間隔のうち前記温度センサによって検出された温度に対応する間隔で前記メモリのリフレッシュ動作を行うように制御する、請求項1~3の何れかに記載の半導体記憶装置。 - 前記制御部は、
前記複数の間隔のうち前記温度センサによって検出された温度に対応する間隔のリフレッシュトリガ信号を出力する第1セレクタと、
制御信号に基づいて、前記温度センサによって検出された温度に対応する間隔のリフレッシュトリガ信号、又は、前記最短の間隔のリフレッシュトリガ信号を出力する第2セレクタと、
前記メモリに対する読み出し又は書き込みアクセスが要求された場合に、前記所定の条件を満たすまで前記最短の間隔のリフレッシュトリガ信号が前記第2セレクタから出力されるように、前記制御信号を生成して前記第2セレクタに出力する回路部と、を備える、請求項4に記載の半導体記憶装置。 - 前記制御部は、
制御信号に基づいて、前記複数の間隔のうち前記温度センサによって検出された温度に対応する間隔のリフレッシュトリガ信号を出力するセレクタと、
前記メモリに対する読み出し又は書き込みアクセスが要求された場合に、前記所定の条件を満たすまで前記最短の間隔のリフレッシュトリガ信号が前記セレクタから出力されるように、前記制御信号を生成して前記セレクタに出力する回路部と、を備える、請求項4に記載の半導体記憶装置。 - 前記制御部は、前記温度センサによって検出された温度が高くなるほどより短い間隔で前記メモリのリフレッシュ動作を行うように制御する、請求項4~6の何れかに記載の半導体記憶装置。
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JP2020148108A JP6975298B1 (ja) | 2020-09-03 | 2020-09-03 | 半導体記憶装置 |
US17/387,757 US11545207B2 (en) | 2020-09-03 | 2021-07-28 | Semiconductor memory device |
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US11798609B2 (en) * | 2021-08-06 | 2023-10-24 | Winbond Electronics Corp. | Semiconductor memory device including control unit controlling time interval of refresh operation on memory to shorten interval between memory refresh operations corresponding to read/write access requirement |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7032071B2 (en) | 2002-05-21 | 2006-04-18 | Sun Microsystems, Inc. | Method, system, and program for using buffers to provide property value information for a device |
US20050036380A1 (en) | 2003-08-14 | 2005-02-17 | Yuan-Mou Su | Method and system of adjusting DRAM refresh interval |
US9589606B2 (en) | 2014-01-15 | 2017-03-07 | Samsung Electronics Co., Ltd. | Handling maximum activation count limit and target row refresh in DDR4 SDRAM |
CN106133700A (zh) | 2014-03-29 | 2016-11-16 | 英派尔科技开发有限公司 | 节能的动态dram缓存调整 |
JP2015219938A (ja) * | 2014-05-21 | 2015-12-07 | マイクロン テクノロジー, インク. | 半導体装置 |
KR102315277B1 (ko) * | 2014-11-03 | 2021-10-20 | 삼성전자 주식회사 | 리프레쉬 특성이 개선된 반도체 메모리 장치 |
JP2016212934A (ja) * | 2015-05-01 | 2016-12-15 | マイクロン テクノロジー, インク. | 半導体装置及びその制御方法 |
US20170110178A1 (en) | 2015-09-17 | 2017-04-20 | Intel Corporation | Hybrid refresh with hidden refreshes and external refreshes |
KR102354987B1 (ko) | 2015-10-22 | 2022-01-24 | 삼성전자주식회사 | 온도에 따라 셀프 리프레쉬 사이클을 제어하는 리프레쉬 방법 |
KR102432701B1 (ko) | 2015-11-18 | 2022-08-16 | 에스케이하이닉스 주식회사 | 리프레시 액티브 제어회로 및 이를 포함하는 메모리 장치 |
US9741421B1 (en) | 2016-04-05 | 2017-08-22 | Micron Technology, Inc. | Refresh circuitry |
KR102468728B1 (ko) * | 2016-08-23 | 2022-11-21 | 에스케이하이닉스 주식회사 | 리프레쉬 제어 회로, 반도체 메모리 장치 및 그의 동작 방법 |
KR102308778B1 (ko) * | 2017-05-24 | 2021-10-05 | 삼성전자주식회사 | 디스터브 로우를 케어하는 메모리 장치 및 그 동작방법 |
US11250902B2 (en) * | 2019-09-26 | 2022-02-15 | Intel Corporation | Method and apparatus to reduce power consumption for refresh of memory devices on a memory module |
US10957376B1 (en) * | 2019-12-18 | 2021-03-23 | Winbond Electronics Corp. | Refresh testing circuit and method |
US11139016B1 (en) * | 2020-04-07 | 2021-10-05 | Micron Technology, Inc. | Read refresh operation |
KR20210149445A (ko) * | 2020-06-02 | 2021-12-09 | 삼성전자주식회사 | 메모리 모듈 및 메모리 모듈의 동작 방법 |
CN114121074B (zh) * | 2020-08-31 | 2023-09-01 | 长鑫存储技术有限公司 | 存储阵列自刷新频率测试方法与存储阵列测试设备 |
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US20220068362A1 (en) | 2022-03-03 |
US11545207B2 (en) | 2023-01-03 |
JP6975298B1 (ja) | 2021-12-01 |
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