JP2021530101A5 - - Google Patents
Info
- Publication number
- JP2021530101A5 JP2021530101A5 JP2020571839A JP2020571839A JP2021530101A5 JP 2021530101 A5 JP2021530101 A5 JP 2021530101A5 JP 2020571839 A JP2020571839 A JP 2020571839A JP 2020571839 A JP2020571839 A JP 2020571839A JP 2021530101 A5 JP2021530101 A5 JP 2021530101A5
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- layer
- conductive
- forming
- interconnection
- Prior art date
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862690838P | 2018-06-27 | 2018-06-27 | |
| US62/690,838 | 2018-06-27 | ||
| PCT/US2019/039260 WO2020006087A1 (en) | 2018-06-27 | 2019-06-26 | Fully self-aligned via with selective bilayer dielectric regrowth |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2021530101A JP2021530101A (ja) | 2021-11-04 |
| JP2021530101A5 true JP2021530101A5 (https=) | 2022-03-07 |
| JPWO2020006087A5 JPWO2020006087A5 (https=) | 2022-03-07 |
| JP7339481B2 JP7339481B2 (ja) | 2023-09-06 |
Family
ID=68987240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020571839A Active JP7339481B2 (ja) | 2018-06-27 | 2019-06-26 | 選択的二重層誘電体再成長を用いた完全な自己整合ビア |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11031287B2 (https=) |
| JP (1) | JP7339481B2 (https=) |
| KR (1) | KR102726634B1 (https=) |
| CN (1) | CN112368822B (https=) |
| TW (1) | TWI816819B (https=) |
| WO (1) | WO2020006087A1 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG11202009105YA (en) * | 2018-03-20 | 2020-10-29 | Tokyo Electron Ltd | Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same |
| US11121025B2 (en) * | 2018-09-27 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layer for side wall passivation |
| US11515203B2 (en) | 2020-02-05 | 2022-11-29 | Tokyo Electron Limited | Selective deposition of conductive cap for fully-aligned-via (FAV) |
| US11508572B2 (en) | 2020-04-01 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| KR20230026385A (ko) * | 2020-06-17 | 2023-02-24 | 도쿄엘렉트론가부시키가이샤 | 영역 선택적 증착에서 측방 막 형성을 감소시키는 방법 |
| US20220238323A1 (en) * | 2021-01-28 | 2022-07-28 | Tokyo Electron Limited | Method for selective deposition of dielectric on dielectric |
| US11929314B2 (en) * | 2021-03-12 | 2024-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures including a fin structure and a metal cap |
| US12564027B2 (en) | 2022-04-27 | 2026-02-24 | Tokyo Electron Limited | Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals |
| US12308310B2 (en) | 2022-05-05 | 2025-05-20 | Nanya Technology Corporation | Method for forming semiconductor interconnection structure against stress migration |
| US12283518B2 (en) | 2022-05-25 | 2025-04-22 | Nanya Technology Corporation | Method for fabricating semiconductor device with contact structure |
| US12417982B2 (en) | 2022-05-25 | 2025-09-16 | Nanya Technology Corporation | Semiconductor device with contact structure |
| TWI833263B (zh) * | 2022-05-25 | 2024-02-21 | 南亞科技股份有限公司 | 具有插塞結構的半導體元件 |
| US20250054809A1 (en) * | 2023-08-07 | 2025-02-13 | Tokyo Electron Limited | Fully self-aligned via with graphene cap |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| JP4910231B2 (ja) * | 2000-10-25 | 2012-04-04 | ソニー株式会社 | 半導体装置の製造方法 |
| US20030148618A1 (en) | 2002-02-07 | 2003-08-07 | Applied Materials, Inc. | Selective metal passivated copper interconnect with zero etch stops |
| US20050082089A1 (en) * | 2003-10-18 | 2005-04-21 | Stephan Grunow | Stacked interconnect structure between copper lines of a semiconductor circuit |
| TWI220774B (en) * | 2003-11-03 | 2004-09-01 | Univ Nat Sun Yat Sen | Method for patterning low dielectric constant film and method for manufacturing dual damascene structure |
| KR100590205B1 (ko) * | 2004-01-12 | 2006-06-15 | 삼성전자주식회사 | 반도체 장치의 배선 구조체 및 그 형성 방법 |
| US7259463B2 (en) | 2004-12-03 | 2007-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Damascene interconnect structure with cap layer |
| US20070228571A1 (en) * | 2006-04-04 | 2007-10-04 | Chen-Hua Yu | Interconnect structure having a silicide/germanide cap layer |
| KR100790452B1 (ko) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
| US7776743B2 (en) * | 2008-07-30 | 2010-08-17 | Tel Epion Inc. | Method of forming semiconductor devices containing metal cap layers |
| KR100953736B1 (ko) * | 2009-07-27 | 2010-04-19 | 주식회사 아토 | 증착 장치 및 반도체 소자의 제조 방법 |
| TWI424529B (zh) * | 2010-10-28 | 2014-01-21 | 旺宏電子股份有限公司 | 半導體結構及其製造方法 |
| JP5665557B2 (ja) * | 2011-01-14 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
| US9269612B2 (en) * | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
| US8803321B2 (en) * | 2012-06-07 | 2014-08-12 | International Business Machines Corporation | Dual damascene dual alignment interconnect scheme |
| US8652962B2 (en) * | 2012-06-19 | 2014-02-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| US9583429B2 (en) * | 2013-11-14 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming same |
| US9659857B2 (en) * | 2013-12-13 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method making the same |
| US9553017B2 (en) | 2015-01-23 | 2017-01-24 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures |
| DE102015114405A1 (de) * | 2015-08-28 | 2017-03-02 | Infineon Technologies Dresden Gmbh | Halbleitervorrichtung mit sich durch eine zwischenschicht erstreckenden kontaktstrukturen und herstellungsverfahren |
| US9659864B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
| KR102616823B1 (ko) * | 2015-12-16 | 2023-12-22 | 삼성전자주식회사 | 반도체 장치 |
| US9530691B1 (en) * | 2016-02-19 | 2016-12-27 | Globalfoundries Inc. | Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias |
| US10068764B2 (en) | 2016-09-13 | 2018-09-04 | Tokyo Electron Limited | Selective metal oxide deposition using a self-assembled monolayer surface pretreatment |
| KR102449200B1 (ko) * | 2017-07-04 | 2022-09-30 | 삼성디스플레이 주식회사 | 클럭 배선을 포함하는 표시 장치 |
| SG11202009105YA (en) * | 2018-03-20 | 2020-10-29 | Tokyo Electron Ltd | Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same |
-
2019
- 2019-06-26 KR KR1020207036487A patent/KR102726634B1/ko active Active
- 2019-06-26 CN CN201980042746.XA patent/CN112368822B/zh active Active
- 2019-06-26 WO PCT/US2019/039260 patent/WO2020006087A1/en not_active Ceased
- 2019-06-26 US US16/453,473 patent/US11031287B2/en active Active
- 2019-06-26 JP JP2020571839A patent/JP7339481B2/ja active Active
- 2019-06-27 TW TW108122579A patent/TWI816819B/zh active
-
2021
- 2021-04-06 US US17/223,831 patent/US11705369B2/en active Active
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