JP2021515232A5 - - Google Patents
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- Publication number
- JP2021515232A5 JP2021515232A5 JP2020546371A JP2020546371A JP2021515232A5 JP 2021515232 A5 JP2021515232 A5 JP 2021515232A5 JP 2020546371 A JP2020546371 A JP 2020546371A JP 2020546371 A JP2020546371 A JP 2020546371A JP 2021515232 A5 JP2021515232 A5 JP 2021515232A5
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Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862639603P | 2018-03-07 | 2018-03-07 | |
| US62/639,603 | 2018-03-07 | ||
| US15/969,158 | 2018-05-02 | ||
| US15/969,158 US10446367B2 (en) | 2018-03-07 | 2018-05-02 | Scan strategies to minimize charging effects and radiation damage of charged particle beam metrology system |
| PCT/US2019/020630 WO2019173252A1 (en) | 2018-03-07 | 2019-03-05 | Scan strategies to minimize charging effects and radiation damage of charged particle beam metrology system |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2021515232A JP2021515232A (ja) | 2021-06-17 |
| JP2021515232A5 true JP2021515232A5 (https=) | 2022-02-16 |
| JPWO2019173252A5 JPWO2019173252A5 (https=) | 2022-02-16 |
| JP7175319B2 JP7175319B2 (ja) | 2022-11-18 |
Family
ID=67843378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020546371A Active JP7175319B2 (ja) | 2018-03-07 | 2019-03-05 | 荷電粒子ビーム計測システムの帯電効果と放射線損傷を最小化する走査戦略 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US10446367B2 (https=) |
| EP (1) | EP3762779B1 (https=) |
| JP (1) | JP7175319B2 (https=) |
| KR (1) | KR102438826B1 (https=) |
| CN (2) | CN121115423A (https=) |
| IL (1) | IL276810B2 (https=) |
| SG (1) | SG11202008092QA (https=) |
| WO (1) | WO2019173252A1 (https=) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11605550B2 (en) * | 2018-12-21 | 2023-03-14 | Xia Tai Xin Semiconductor (Qing Dao) Ltd. | Alignment system |
| JP2021093336A (ja) * | 2019-12-12 | 2021-06-17 | 株式会社日立ハイテク | 画像調整方法および荷電粒子ビームシステム |
| US11874102B2 (en) * | 2019-12-30 | 2024-01-16 | Kla Corporation | Thick photo resist layer metrology target |
| KR102857305B1 (ko) * | 2020-02-07 | 2025-09-08 | 케이엘에이 코포레이션 | 반도체 디바이스의 오정합 측정에서의 비직교 타겟 및 이를 사용하기 위한 방법 |
| CN115428139B (zh) * | 2020-04-15 | 2024-04-12 | 科磊股份有限公司 | 可用于测量半导体装置偏移的具有装置级特征的偏移目标 |
| US11054753B1 (en) * | 2020-04-20 | 2021-07-06 | Applied Materials Israel Ltd. | Overlay monitoring |
| CN115485824B (zh) * | 2020-05-05 | 2024-04-16 | 科磊股份有限公司 | 用于高表面型态半导体堆叠的计量目标 |
| WO2021225587A1 (en) * | 2020-05-06 | 2021-11-11 | Kla Corporation | Inter-step feedforward process control in the manufacture of semiconductor devices |
| US11686576B2 (en) * | 2020-06-04 | 2023-06-27 | Kla Corporation | Metrology target for one-dimensional measurement of periodic misregistration |
| US12100574B2 (en) | 2020-07-01 | 2024-09-24 | Kla Corporation | Target and algorithm to measure overlay by modeling back scattering electrons on overlapping structures |
| JP7144485B2 (ja) * | 2020-07-15 | 2022-09-29 | 日本電子株式会社 | 像取得方法および電子顕微鏡 |
| US11995848B2 (en) * | 2021-03-22 | 2024-05-28 | Applied Materials Israel Ltd. | Image generation for examination of a semiconductor specimen |
| KR102617622B1 (ko) * | 2021-04-26 | 2023-12-27 | (주)오로스 테크놀로지 | 오버레이 마크 및 이를 이용한 오버레이 계측방법 및 반도체 디바이스 제조방법 |
| KR102750903B1 (ko) * | 2021-06-30 | 2025-01-09 | (주) 오로스테크놀로지 | 오버레이 마크 및 이를 이용한 오버레이 계측방법 및 반도체 디바이스 제조방법 |
| KR102750914B1 (ko) * | 2021-06-30 | 2025-01-09 | (주) 오로스테크놀로지 | 오버레이 마크 및 이를 이용한 오버레이 계측방법 및 반도체 디바이스 제조방법 |
| KR102750923B1 (ko) * | 2021-06-30 | 2025-01-09 | (주) 오로스테크놀로지 | 오버레이 마크 및 이를 이용한 오버레이 계측방법 및 반도체 디바이스 제조방법 |
| US12461456B2 (en) * | 2022-01-28 | 2025-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for overlay measurement in semiconductor device manufacturing |
| TW202414771A (zh) * | 2022-09-29 | 2024-04-01 | 聯華電子股份有限公司 | 疊對圖樣 |
| US20240167813A1 (en) * | 2022-11-23 | 2024-05-23 | Kla Corporation | System and method for suppression of tool induced shift in scanning overlay metrology |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0774079A (ja) * | 1993-09-02 | 1995-03-17 | Nikon Corp | 露光方法及び露光装置 |
| JP3148353B2 (ja) | 1991-05-30 | 2001-03-19 | ケーエルエー・インストルメンツ・コーポレーション | 電子ビーム検査方法とそのシステム |
| JP2000077300A (ja) * | 1998-08-28 | 2000-03-14 | Nikon Corp | 投影露光装置及び位置検出方法 |
| JP2001189263A (ja) | 1999-12-28 | 2001-07-10 | Toshiba Corp | 合わせずれ検査方法及び荷電ビーム露光方法 |
| US7541201B2 (en) | 2000-08-30 | 2009-06-02 | Kla-Tencor Technologies Corporation | Apparatus and methods for determining overlay of structures having rotational or mirror symmetry |
| JP5180419B2 (ja) * | 2000-08-30 | 2013-04-10 | ケーエルエー−テンカー・コーポレーション | 重ね合わせマーク、重ね合わせマークの設計方法および重ね合わせ測定の方法 |
| US7001830B2 (en) | 2003-09-02 | 2006-02-21 | Advanced Micro Devices, Inc | System and method of pattern recognition and metrology structure for an X-initiative layout design |
| JP2005183577A (ja) * | 2003-12-18 | 2005-07-07 | Sony Corp | 露光装置、露光方法、および半導体装置の製造方法 |
| JP4734261B2 (ja) * | 2004-02-18 | 2011-07-27 | ケーエルエー−テンカー コーポレイション | 連続変化するオフセットマークと、オーバレイ決定方法 |
| US7808643B2 (en) * | 2005-02-25 | 2010-10-05 | Nanometrics Incorporated | Determining overlay error using an in-chip overlay target |
| US7477396B2 (en) * | 2005-02-25 | 2009-01-13 | Nanometrics Incorporated | Methods and systems for determining overlay error based on target image symmetry |
| DE102008064504B4 (de) * | 2008-12-22 | 2011-04-07 | Carl Zeiss Smt Gmbh | Projektionsbelichtungsverfahren und Projektionsbelichtungsanlage für die Mikrolithographie |
| EP2458441B1 (en) * | 2010-11-30 | 2022-01-19 | ASML Netherlands BV | Measuring method, apparatus and substrate |
| JP6002480B2 (ja) * | 2012-07-06 | 2016-10-05 | 株式会社日立ハイテクノロジーズ | オーバーレイ誤差測定装置、及びパターン測定をコンピューターに実行させるコンピュータープログラム |
| US9214317B2 (en) * | 2013-06-04 | 2015-12-15 | Kla-Tencor Corporation | System and method of SEM overlay metrology |
| JP6378927B2 (ja) | 2014-04-25 | 2018-08-22 | 株式会社日立ハイテクノロジーズ | 計測システムおよび計測方法 |
| EP3171396A1 (en) * | 2015-11-18 | 2017-05-24 | Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO | Method of determining an overlay error, manufacturing method and system for manufacturing of a multilayer semiconductor device, and semiconductor device manufactured thereby |
-
2018
- 2018-05-02 US US15/969,158 patent/US10446367B2/en active Active
-
2019
- 2019-03-05 CN CN202511422236.9A patent/CN121115423A/zh active Pending
- 2019-03-05 SG SG11202008092QA patent/SG11202008092QA/en unknown
- 2019-03-05 CN CN201980016988.1A patent/CN111801626A/zh active Pending
- 2019-03-05 JP JP2020546371A patent/JP7175319B2/ja active Active
- 2019-03-05 KR KR1020207028710A patent/KR102438826B1/ko active Active
- 2019-03-05 EP EP19764082.4A patent/EP3762779B1/en active Active
- 2019-03-05 WO PCT/US2019/020630 patent/WO2019173252A1/en not_active Ceased
-
2020
- 2020-08-19 IL IL276810A patent/IL276810B2/en unknown
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