JP2021508905A - フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法 - Google Patents

フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法 Download PDF

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JP2021508905A
JP2021508905A JP2020534193A JP2020534193A JP2021508905A JP 2021508905 A JP2021508905 A JP 2021508905A JP 2020534193 A JP2020534193 A JP 2020534193A JP 2020534193 A JP2020534193 A JP 2020534193A JP 2021508905 A JP2021508905 A JP 2021508905A
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memory cells
volatile memory
programming
programmed
rows
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JP2021508905A5 (https=
Inventor
ティワリ、ビピン
ドー、ナン
バン トラン、ヒュー
バン トラン、ヒュー
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Publication of JP2021508905A publication Critical patent/JP2021508905A/ja
Publication of JP2021508905A5 publication Critical patent/JP2021508905A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2020534193A 2017-12-20 2018-11-13 フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法 Pending JP2021508905A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/849,268 US10600484B2 (en) 2017-12-20 2017-12-20 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
US15/849,268 2017-12-20
PCT/US2018/060850 WO2019125650A1 (en) 2017-12-20 2018-11-13 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory

Publications (2)

Publication Number Publication Date
JP2021508905A true JP2021508905A (ja) 2021-03-11
JP2021508905A5 JP2021508905A5 (https=) 2021-12-09

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JP2020534193A Pending JP2021508905A (ja) 2017-12-20 2018-11-13 フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法

Country Status (7)

Country Link
US (2) US10600484B2 (https=)
EP (1) EP3729276A4 (https=)
JP (1) JP2021508905A (https=)
KR (1) KR102352387B1 (https=)
CN (1) CN111492352A (https=)
TW (1) TWI687928B (https=)
WO (1) WO2019125650A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102703487B1 (ko) * 2018-08-03 2024-09-06 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10998325B2 (en) * 2018-12-03 2021-05-04 Silicon Storage Technology, Inc. Memory cell with floating gate, coupling gate and erase gate, and method of making same
CN114335186B (zh) 2020-09-30 2025-02-07 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11232886A (ja) * 1998-02-16 1999-08-27 Hitachi Ltd 半導体装置、メモリカード及びデータ処理システム
US20050146932A1 (en) * 2003-12-31 2005-07-07 Chien-Hsing Lee [nonvolatile memory structure]
JP2008257781A (ja) * 2007-04-03 2008-10-23 Toshiba Corp 半導体記憶装置のデータ書き込み方法
US20160035427A1 (en) * 2014-07-29 2016-02-04 Jae-Duk Yu Data storage device and operation method thereof
US20170125101A1 (en) * 2015-10-28 2017-05-04 SanDisk Technologies, Inc. Program sequencing

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US5619453A (en) * 1995-07-28 1997-04-08 Micron Quantum Devices, Inc. Memory system having programmable flow control register
US6400624B1 (en) * 2001-02-26 2002-06-04 Advanced Micro Devices, Inc. Configure registers and loads to tailor a multi-level cell flash design
US6781877B2 (en) * 2002-09-06 2004-08-24 Sandisk Corporation Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
US7630237B2 (en) * 2003-02-06 2009-12-08 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
KR20060067955A (ko) * 2003-08-13 2006-06-20 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 비휘발성 전하 트래핑 메모리 장치의 어레이의 작동 방법및 전기적 장치
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
US7120051B2 (en) 2004-12-14 2006-10-10 Sandisk Corporation Pipelined programming of non-volatile memories using early data
US7802064B2 (en) 2006-03-31 2010-09-21 Mosaid Technologies Incorporated Flash memory system control scheme
KR100763353B1 (ko) * 2006-04-26 2007-10-04 삼성전자주식회사 인접하는 메모리셀과의 커플링 노이즈를 저감시키는불휘발성 반도체 메모리 장치
KR100816121B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리장치의 멀티비트 프로그램 방법
US7898863B2 (en) * 2007-08-01 2011-03-01 Micron Technology, Inc. Method, apparatus, and system for improved read operation in memory
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8300478B2 (en) * 2007-09-19 2012-10-30 Apple Inc. Reducing distortion using joint storage
US8174905B2 (en) * 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
KR101438666B1 (ko) * 2008-03-25 2014-11-03 삼성전자주식회사 전하의 측면 이동을 줄일 수 있는 메모리 장치의 작동 방법
US8539311B2 (en) * 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
EP2418584A1 (en) 2010-08-13 2012-02-15 Thomson Licensing Method and apparatus for storing at least two data streams into an array of memories, or for reading at least two data streams from an array of memories
US8395936B2 (en) * 2011-05-09 2013-03-12 Sandisk Technologies Inc. Using channel-to-channel coupling to compensate floating gate-to-floating gate coupling in programming of non-volatile memory
KR101775660B1 (ko) 2011-09-29 2017-09-07 삼성전자주식회사 워드 라인 전압의 변화없이 상이한 문턱 전압들을 갖는 메모리 셀들을 읽는 방법 및 그것을 이용한 불 휘발성 메모리 장치
KR101927212B1 (ko) * 2012-05-09 2019-03-07 삼성전자주식회사 비휘발성 메모리 장치의 프로그래밍 방법
KR102106866B1 (ko) * 2013-01-29 2020-05-06 삼성전자주식회사 멀티레벨 불휘발성 메모리 장치 및 프로그램 방법
US10134475B2 (en) * 2015-03-31 2018-11-20 Silicon Storage Technology, Inc. Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system
US9633719B2 (en) * 2015-05-29 2017-04-25 Micron Technology, Inc. Programming memory cells to be programmed to different levels to an intermediate level from a lowest level

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11232886A (ja) * 1998-02-16 1999-08-27 Hitachi Ltd 半導体装置、メモリカード及びデータ処理システム
US20050146932A1 (en) * 2003-12-31 2005-07-07 Chien-Hsing Lee [nonvolatile memory structure]
JP2008257781A (ja) * 2007-04-03 2008-10-23 Toshiba Corp 半導体記憶装置のデータ書き込み方法
US20160035427A1 (en) * 2014-07-29 2016-02-04 Jae-Duk Yu Data storage device and operation method thereof
US20170125101A1 (en) * 2015-10-28 2017-05-04 SanDisk Technologies, Inc. Program sequencing

Also Published As

Publication number Publication date
CN111492352A (zh) 2020-08-04
US20190189214A1 (en) 2019-06-20
US20200176060A1 (en) 2020-06-04
TWI687928B (zh) 2020-03-11
EP3729276A1 (en) 2020-10-28
US10600484B2 (en) 2020-03-24
TW201939505A (zh) 2019-10-01
EP3729276A4 (en) 2021-08-25
WO2019125650A1 (en) 2019-06-27
KR20200077566A (ko) 2020-06-30
KR102352387B1 (ko) 2022-01-17
US10699787B2 (en) 2020-06-30

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