KR102352387B1 - 플래시 메모리에서의 프로그래밍 동안 플로팅 게이트와 플로팅 게이트 간의 커플링 효과들을 최소화시키기 위한 시스템 및 방법 - Google Patents

플래시 메모리에서의 프로그래밍 동안 플로팅 게이트와 플로팅 게이트 간의 커플링 효과들을 최소화시키기 위한 시스템 및 방법 Download PDF

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KR102352387B1
KR102352387B1 KR1020207015303A KR20207015303A KR102352387B1 KR 102352387 B1 KR102352387 B1 KR 102352387B1 KR 1020207015303 A KR1020207015303 A KR 1020207015303A KR 20207015303 A KR20207015303 A KR 20207015303A KR 102352387 B1 KR102352387 B1 KR 102352387B1
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memory cells
volatile memory
programming
rows
programmed
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KR20200077566A (ko
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비핀 티와리
난 도
휴 반 트란
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실리콘 스토리지 테크놀로지 인크
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H01L29/42328—
    • H01L29/7885—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020207015303A 2017-12-20 2018-11-13 플래시 메모리에서의 프로그래밍 동안 플로팅 게이트와 플로팅 게이트 간의 커플링 효과들을 최소화시키기 위한 시스템 및 방법 Active KR102352387B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/849,268 US10600484B2 (en) 2017-12-20 2017-12-20 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
US15/849,268 2017-12-20
PCT/US2018/060850 WO2019125650A1 (en) 2017-12-20 2018-11-13 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory

Publications (2)

Publication Number Publication Date
KR20200077566A KR20200077566A (ko) 2020-06-30
KR102352387B1 true KR102352387B1 (ko) 2022-01-17

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Country Link
US (2) US10600484B2 (https=)
EP (1) EP3729276A4 (https=)
JP (1) JP2021508905A (https=)
KR (1) KR102352387B1 (https=)
CN (1) CN111492352A (https=)
TW (1) TWI687928B (https=)
WO (1) WO2019125650A1 (https=)

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KR102703487B1 (ko) * 2018-08-03 2024-09-06 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10998325B2 (en) * 2018-12-03 2021-05-04 Silicon Storage Technology, Inc. Memory cell with floating gate, coupling gate and erase gate, and method of making same
CN114335186B (zh) 2020-09-30 2025-02-07 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法

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KR100816121B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리장치의 멀티비트 프로그램 방법
US20140211565A1 (en) 2013-01-29 2014-07-31 Jung-ho Song Methods of programming multi-level cell nonvolatile memory devices and devices so operating

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KR20060067955A (ko) * 2003-08-13 2006-06-20 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 비휘발성 전하 트래핑 메모리 장치의 어레이의 작동 방법및 전기적 장치
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KR100816121B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리장치의 멀티비트 프로그램 방법
US20140211565A1 (en) 2013-01-29 2014-07-31 Jung-ho Song Methods of programming multi-level cell nonvolatile memory devices and devices so operating

Also Published As

Publication number Publication date
CN111492352A (zh) 2020-08-04
US20190189214A1 (en) 2019-06-20
JP2021508905A (ja) 2021-03-11
US20200176060A1 (en) 2020-06-04
TWI687928B (zh) 2020-03-11
EP3729276A1 (en) 2020-10-28
US10600484B2 (en) 2020-03-24
TW201939505A (zh) 2019-10-01
EP3729276A4 (en) 2021-08-25
WO2019125650A1 (en) 2019-06-27
KR20200077566A (ko) 2020-06-30
US10699787B2 (en) 2020-06-30

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