CN111492352A - 用于在闪存存储器中编程期间使浮栅到浮栅耦合效应最小化的系统和方法 - Google Patents

用于在闪存存储器中编程期间使浮栅到浮栅耦合效应最小化的系统和方法 Download PDF

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Publication number
CN111492352A
CN111492352A CN201880081371.3A CN201880081371A CN111492352A CN 111492352 A CN111492352 A CN 111492352A CN 201880081371 A CN201880081371 A CN 201880081371A CN 111492352 A CN111492352 A CN 111492352A
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CN
China
Prior art keywords
memory cells
programmed
volatile memory
data
rows
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Pending
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CN201880081371.3A
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English (en)
Chinese (zh)
Inventor
V·蒂瓦里
N·多
H·V·特兰
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Application filed by Silicon Storage Technology Inc filed Critical Silicon Storage Technology Inc
Publication of CN111492352A publication Critical patent/CN111492352A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CN201880081371.3A 2017-12-20 2018-11-13 用于在闪存存储器中编程期间使浮栅到浮栅耦合效应最小化的系统和方法 Pending CN111492352A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/849,268 US10600484B2 (en) 2017-12-20 2017-12-20 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
US15/849,268 2017-12-20
PCT/US2018/060850 WO2019125650A1 (en) 2017-12-20 2018-11-13 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory

Publications (1)

Publication Number Publication Date
CN111492352A true CN111492352A (zh) 2020-08-04

Family

ID=66816257

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880081371.3A Pending CN111492352A (zh) 2017-12-20 2018-11-13 用于在闪存存储器中编程期间使浮栅到浮栅耦合效应最小化的系统和方法

Country Status (7)

Country Link
US (2) US10600484B2 (https=)
EP (1) EP3729276A4 (https=)
JP (1) JP2021508905A (https=)
KR (1) KR102352387B1 (https=)
CN (1) CN111492352A (https=)
TW (1) TWI687928B (https=)
WO (1) WO2019125650A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102703487B1 (ko) * 2018-08-03 2024-09-06 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10998325B2 (en) * 2018-12-03 2021-05-04 Silicon Storage Technology, Inc. Memory cell with floating gate, coupling gate and erase gate, and method of making same
CN114335186B (zh) 2020-09-30 2025-02-07 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619453A (en) * 1995-07-28 1997-04-08 Micron Quantum Devices, Inc. Memory system having programmable flow control register
US20050018482A1 (en) * 2002-09-06 2005-01-27 Raul-Adrian Cemea Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
CN1836289A (zh) * 2003-08-13 2006-09-20 皇家飞利浦电子股份有限公司 改进的电荷俘获非易失性存储器的擦除和读取方案
CN101233577A (zh) * 2005-08-02 2008-07-30 桑迪士克股份有限公司 对非易失性集成存储器装置中的单元进行编程的系统和方法
US20100157675A1 (en) * 2007-09-19 2010-06-24 Anobit Technologies Ltd Programming orders for reducing distortion in arrays of multi-level analog memory cells
US20120287716A1 (en) * 2011-05-09 2012-11-15 Haibo Li Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory
US20170125101A1 (en) * 2015-10-28 2017-05-04 SanDisk Technologies, Inc. Program sequencing
US20170178737A1 (en) * 2015-05-29 2017-06-22 Micron Technology, Inc. Programming memory cells to be programmed to different levels to an intermediate level from a lowest level

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
JP3883687B2 (ja) * 1998-02-16 2007-02-21 株式会社ルネサステクノロジ 半導体装置、メモリカード及びデータ処理システム
US6400624B1 (en) * 2001-02-26 2002-06-04 Advanced Micro Devices, Inc. Configure registers and loads to tailor a multi-level cell flash design
US7046549B2 (en) * 2003-12-31 2006-05-16 Solid State System Co., Ltd. Nonvolatile memory structure
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
US7120051B2 (en) 2004-12-14 2006-10-10 Sandisk Corporation Pipelined programming of non-volatile memories using early data
US7802064B2 (en) 2006-03-31 2010-09-21 Mosaid Technologies Incorporated Flash memory system control scheme
KR100763353B1 (ko) * 2006-04-26 2007-10-04 삼성전자주식회사 인접하는 메모리셀과의 커플링 노이즈를 저감시키는불휘발성 반도체 메모리 장치
KR100816121B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리장치의 멀티비트 프로그램 방법
JP4435200B2 (ja) * 2007-04-03 2010-03-17 株式会社東芝 半導体記憶装置のデータ書き込み方法
US7898863B2 (en) * 2007-08-01 2011-03-01 Micron Technology, Inc. Method, apparatus, and system for improved read operation in memory
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8300478B2 (en) * 2007-09-19 2012-10-30 Apple Inc. Reducing distortion using joint storage
KR101438666B1 (ko) * 2008-03-25 2014-11-03 삼성전자주식회사 전하의 측면 이동을 줄일 수 있는 메모리 장치의 작동 방법
US8539311B2 (en) * 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
EP2418584A1 (en) 2010-08-13 2012-02-15 Thomson Licensing Method and apparatus for storing at least two data streams into an array of memories, or for reading at least two data streams from an array of memories
KR101775660B1 (ko) 2011-09-29 2017-09-07 삼성전자주식회사 워드 라인 전압의 변화없이 상이한 문턱 전압들을 갖는 메모리 셀들을 읽는 방법 및 그것을 이용한 불 휘발성 메모리 장치
KR101927212B1 (ko) * 2012-05-09 2019-03-07 삼성전자주식회사 비휘발성 메모리 장치의 프로그래밍 방법
KR102106866B1 (ko) * 2013-01-29 2020-05-06 삼성전자주식회사 멀티레벨 불휘발성 메모리 장치 및 프로그램 방법
KR102234592B1 (ko) * 2014-07-29 2021-04-05 삼성전자주식회사 불휘발성 메모리, 데이터 저장 장치, 및 데이터 저장 장치의 동작 방법
US10134475B2 (en) * 2015-03-31 2018-11-20 Silicon Storage Technology, Inc. Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619453A (en) * 1995-07-28 1997-04-08 Micron Quantum Devices, Inc. Memory system having programmable flow control register
US20050018482A1 (en) * 2002-09-06 2005-01-27 Raul-Adrian Cemea Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
CN1836289A (zh) * 2003-08-13 2006-09-20 皇家飞利浦电子股份有限公司 改进的电荷俘获非易失性存储器的擦除和读取方案
CN101233577A (zh) * 2005-08-02 2008-07-30 桑迪士克股份有限公司 对非易失性集成存储器装置中的单元进行编程的系统和方法
US20100157675A1 (en) * 2007-09-19 2010-06-24 Anobit Technologies Ltd Programming orders for reducing distortion in arrays of multi-level analog memory cells
US20120287716A1 (en) * 2011-05-09 2012-11-15 Haibo Li Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory
US20170178737A1 (en) * 2015-05-29 2017-06-22 Micron Technology, Inc. Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
US20170125101A1 (en) * 2015-10-28 2017-05-04 SanDisk Technologies, Inc. Program sequencing

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Publication number Publication date
US20190189214A1 (en) 2019-06-20
JP2021508905A (ja) 2021-03-11
US20200176060A1 (en) 2020-06-04
TWI687928B (zh) 2020-03-11
EP3729276A1 (en) 2020-10-28
US10600484B2 (en) 2020-03-24
TW201939505A (zh) 2019-10-01
EP3729276A4 (en) 2021-08-25
WO2019125650A1 (en) 2019-06-27
KR20200077566A (ko) 2020-06-30
KR102352387B1 (ko) 2022-01-17
US10699787B2 (en) 2020-06-30

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