TWI687928B - 用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法 - Google Patents

用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法 Download PDF

Info

Publication number
TWI687928B
TWI687928B TW107144336A TW107144336A TWI687928B TW I687928 B TWI687928 B TW I687928B TW 107144336 A TW107144336 A TW 107144336A TW 107144336 A TW107144336 A TW 107144336A TW I687928 B TWI687928 B TW I687928B
Authority
TW
Taiwan
Prior art keywords
memory cells
volatile memory
programmed
rows
programming
Prior art date
Application number
TW107144336A
Other languages
English (en)
Chinese (zh)
Other versions
TW201939505A (zh
Inventor
維平 蒂瓦里
恩漢 杜
曉萬 陳
Original Assignee
美商超捷公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商超捷公司 filed Critical 美商超捷公司
Publication of TW201939505A publication Critical patent/TW201939505A/zh
Application granted granted Critical
Publication of TWI687928B publication Critical patent/TWI687928B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW107144336A 2017-12-20 2018-12-10 用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法 TWI687928B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/849,268 US10600484B2 (en) 2017-12-20 2017-12-20 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
US15/849,268 2017-12-20
PCT/US2018/060850 WO2019125650A1 (en) 2017-12-20 2018-11-13 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
WOPCT/US18/60850 2018-11-13
??PCT/US18/60850 2018-11-13

Publications (2)

Publication Number Publication Date
TW201939505A TW201939505A (zh) 2019-10-01
TWI687928B true TWI687928B (zh) 2020-03-11

Family

ID=66816257

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107144336A TWI687928B (zh) 2017-12-20 2018-12-10 用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法

Country Status (7)

Country Link
US (2) US10600484B2 (https=)
EP (1) EP3729276A4 (https=)
JP (1) JP2021508905A (https=)
KR (1) KR102352387B1 (https=)
CN (1) CN111492352A (https=)
TW (1) TWI687928B (https=)
WO (1) WO2019125650A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102703487B1 (ko) * 2018-08-03 2024-09-06 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10998325B2 (en) * 2018-12-03 2021-05-04 Silicon Storage Technology, Inc. Memory cell with floating gate, coupling gate and erase gate, and method of making same
CN114335186B (zh) 2020-09-30 2025-02-07 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050146932A1 (en) * 2003-12-31 2005-07-07 Chien-Hsing Lee [nonvolatile memory structure]
JP4372196B2 (ja) * 2004-12-14 2009-11-25 サンディスク コーポレイション 初期データを用いる不揮発性メモリのパイプライン形プログラミング
US20130083607A1 (en) * 2011-09-29 2013-04-04 Samsung Electronics Co., Ltd. Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US5619453A (en) * 1995-07-28 1997-04-08 Micron Quantum Devices, Inc. Memory system having programmable flow control register
JP3883687B2 (ja) * 1998-02-16 2007-02-21 株式会社ルネサステクノロジ 半導体装置、メモリカード及びデータ処理システム
US6400624B1 (en) * 2001-02-26 2002-06-04 Advanced Micro Devices, Inc. Configure registers and loads to tailor a multi-level cell flash design
US6781877B2 (en) * 2002-09-06 2004-08-24 Sandisk Corporation Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
US7630237B2 (en) * 2003-02-06 2009-12-08 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
KR20060067955A (ko) * 2003-08-13 2006-06-20 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 비휘발성 전하 트래핑 메모리 장치의 어레이의 작동 방법및 전기적 장치
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
US7802064B2 (en) 2006-03-31 2010-09-21 Mosaid Technologies Incorporated Flash memory system control scheme
KR100763353B1 (ko) * 2006-04-26 2007-10-04 삼성전자주식회사 인접하는 메모리셀과의 커플링 노이즈를 저감시키는불휘발성 반도체 메모리 장치
KR100816121B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리장치의 멀티비트 프로그램 방법
JP4435200B2 (ja) * 2007-04-03 2010-03-17 株式会社東芝 半導体記憶装置のデータ書き込み方法
US7898863B2 (en) * 2007-08-01 2011-03-01 Micron Technology, Inc. Method, apparatus, and system for improved read operation in memory
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8300478B2 (en) * 2007-09-19 2012-10-30 Apple Inc. Reducing distortion using joint storage
US8174905B2 (en) * 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
KR101438666B1 (ko) * 2008-03-25 2014-11-03 삼성전자주식회사 전하의 측면 이동을 줄일 수 있는 메모리 장치의 작동 방법
US8539311B2 (en) * 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
EP2418584A1 (en) 2010-08-13 2012-02-15 Thomson Licensing Method and apparatus for storing at least two data streams into an array of memories, or for reading at least two data streams from an array of memories
US8395936B2 (en) * 2011-05-09 2013-03-12 Sandisk Technologies Inc. Using channel-to-channel coupling to compensate floating gate-to-floating gate coupling in programming of non-volatile memory
KR101927212B1 (ko) * 2012-05-09 2019-03-07 삼성전자주식회사 비휘발성 메모리 장치의 프로그래밍 방법
KR102106866B1 (ko) * 2013-01-29 2020-05-06 삼성전자주식회사 멀티레벨 불휘발성 메모리 장치 및 프로그램 방법
KR102234592B1 (ko) * 2014-07-29 2021-04-05 삼성전자주식회사 불휘발성 메모리, 데이터 저장 장치, 및 데이터 저장 장치의 동작 방법
US10134475B2 (en) * 2015-03-31 2018-11-20 Silicon Storage Technology, Inc. Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system
US9633719B2 (en) * 2015-05-29 2017-04-25 Micron Technology, Inc. Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
US9865352B2 (en) * 2015-10-28 2018-01-09 Sandisk Technologies, Llc Program sequencing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050146932A1 (en) * 2003-12-31 2005-07-07 Chien-Hsing Lee [nonvolatile memory structure]
JP4372196B2 (ja) * 2004-12-14 2009-11-25 サンディスク コーポレイション 初期データを用いる不揮発性メモリのパイプライン形プログラミング
US20130083607A1 (en) * 2011-09-29 2013-04-04 Samsung Electronics Co., Ltd. Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same

Also Published As

Publication number Publication date
CN111492352A (zh) 2020-08-04
US20190189214A1 (en) 2019-06-20
JP2021508905A (ja) 2021-03-11
US20200176060A1 (en) 2020-06-04
EP3729276A1 (en) 2020-10-28
US10600484B2 (en) 2020-03-24
TW201939505A (zh) 2019-10-01
EP3729276A4 (en) 2021-08-25
WO2019125650A1 (en) 2019-06-27
KR20200077566A (ko) 2020-06-30
KR102352387B1 (ko) 2022-01-17
US10699787B2 (en) 2020-06-30

Similar Documents

Publication Publication Date Title
TWI698868B (zh) 具有電容耦合至浮動閘之閘極的記憶體單元之程式化
TWI682393B (zh) 用於在非揮發性記憶體中儲存多位元資料的系統及方法
KR20190003781A (ko) 개별 메모리 셀 판독, 프로그래밍 및 소거를 갖는 플래시 메모리 어레이
JPH09181283A (ja) Ｎａｎｄ型のフラッシュメモリ素子及びその駆動方法
TWI683314B (zh) 具有位元組抹除操作之分離閘快閃記憶體陣列
TWI687928B (zh) 用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法
TWI686808B (zh) 用於在非揮發性記憶體中使用電流乘數儲存並檢索多位元資料的系統及方法
KR102687843B1 (ko) 저장된 인덱스 정보를 갖는 비휘발성 메모리 디바이스