JP2021508905A5 - - Google Patents

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Publication number
JP2021508905A5
JP2021508905A5 JP2020534193A JP2020534193A JP2021508905A5 JP 2021508905 A5 JP2021508905 A5 JP 2021508905A5 JP 2020534193 A JP2020534193 A JP 2020534193A JP 2020534193 A JP2020534193 A JP 2020534193A JP 2021508905 A5 JP2021508905 A5 JP 2021508905A5
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JP
Japan
Prior art keywords
volatile memory
memory cells
rows
programming
values
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020534193A
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English (en)
Japanese (ja)
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JP2021508905A (ja
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Publication date
Priority claimed from US15/849,268 external-priority patent/US10600484B2/en
Application filed filed Critical
Publication of JP2021508905A publication Critical patent/JP2021508905A/ja
Publication of JP2021508905A5 publication Critical patent/JP2021508905A5/ja
Pending legal-status Critical Current

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JP2020534193A 2017-12-20 2018-11-13 フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法 Pending JP2021508905A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/849,268 US10600484B2 (en) 2017-12-20 2017-12-20 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
US15/849,268 2017-12-20
PCT/US2018/060850 WO2019125650A1 (en) 2017-12-20 2018-11-13 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory

Publications (2)

Publication Number Publication Date
JP2021508905A JP2021508905A (ja) 2021-03-11
JP2021508905A5 true JP2021508905A5 (https=) 2021-12-09

Family

ID=66816257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020534193A Pending JP2021508905A (ja) 2017-12-20 2018-11-13 フラッシュメモリ内でのプログラミング中に浮遊ゲート対浮遊ゲートカップリング効果を最小化するためのシステム及び方法

Country Status (7)

Country Link
US (2) US10600484B2 (https=)
EP (1) EP3729276A4 (https=)
JP (1) JP2021508905A (https=)
KR (1) KR102352387B1 (https=)
CN (1) CN111492352A (https=)
TW (1) TWI687928B (https=)
WO (1) WO2019125650A1 (https=)

Families Citing this family (3)

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US10998325B2 (en) * 2018-12-03 2021-05-04 Silicon Storage Technology, Inc. Memory cell with floating gate, coupling gate and erase gate, and method of making same
CN114335186B (zh) 2020-09-30 2025-02-07 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法

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