JP2021507507A5 - - Google Patents

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Publication number
JP2021507507A5
JP2021507507A5 JP2020531528A JP2020531528A JP2021507507A5 JP 2021507507 A5 JP2021507507 A5 JP 2021507507A5 JP 2020531528 A JP2020531528 A JP 2020531528A JP 2020531528 A JP2020531528 A JP 2020531528A JP 2021507507 A5 JP2021507507 A5 JP 2021507507A5
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JP
Japan
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vertical fin
region
forming
well
layer
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JP2020531528A
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English (en)
Japanese (ja)
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JP2021507507A (ja
JP7271054B2 (ja
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Priority claimed from US15/843,786 external-priority patent/US10685886B2/en
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JP2020531528A 2017-12-15 2018-12-03 基板上に論理デバイスおよびパワー・デバイスを形成する方法ならびに基板上の論理デバイスおよびパワー・デバイス Active JP7271054B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/843,786 US10685886B2 (en) 2017-12-15 2017-12-15 Fabrication of logic devices and power devices on the same substrate
US15/843,786 2017-12-15
PCT/IB2018/059558 WO2019116152A1 (en) 2017-12-15 2018-12-03 Fabrication of logic devices and power devices on the same substrate

Publications (3)

Publication Number Publication Date
JP2021507507A JP2021507507A (ja) 2021-02-22
JP2021507507A5 true JP2021507507A5 (https=) 2021-07-26
JP7271054B2 JP7271054B2 (ja) 2023-05-11

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ID=66814713

Family Applications (1)

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JP2020531528A Active JP7271054B2 (ja) 2017-12-15 2018-12-03 基板上に論理デバイスおよびパワー・デバイスを形成する方法ならびに基板上の論理デバイスおよびパワー・デバイス

Country Status (6)

Country Link
US (2) US10685886B2 (https=)
JP (1) JP7271054B2 (https=)
CN (1) CN111433905B (https=)
DE (1) DE112018005623T5 (https=)
GB (1) GB2582087B (https=)
WO (1) WO2019116152A1 (https=)

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US8895327B1 (en) * 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US10832975B2 (en) * 2018-06-12 2020-11-10 International Business Machines Corporation Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement
US10916638B2 (en) * 2018-09-18 2021-02-09 International Business Machines Corporation Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
US12009266B2 (en) * 2019-12-18 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for fringing capacitance control
DE102020202038A1 (de) * 2020-02-18 2021-08-19 Robert Bosch Gesellschaft mit beschränkter Haftung Vertikaler Fin-Feldeffekttransistor, vertikaler Fin-Feldeffekttransistor-Anordnung und Verfahren zum Bilden eines vertikalen Fin-Feldeffekttransistors
US11908907B2 (en) * 2020-12-11 2024-02-20 International Business Machines Corporation VFET contact formation
US11404581B2 (en) * 2020-12-21 2022-08-02 International Business Machines Corporation Wimpy vertical transport field effect transistor with dipole liners
JP7844983B2 (ja) * 2022-03-29 2026-04-14 セイコーエプソン株式会社 半導体装置およびパワーデバイス
US20240071811A1 (en) * 2022-08-25 2024-02-29 International Business Machines Corporation Stacked fet substrate contact
DE102024201914A1 (de) * 2024-03-01 2025-09-04 Robert Bosch Gesellschaft mit beschränkter Haftung Transistorchip und Verfahren zur Herstellung

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US5182619A (en) * 1991-09-03 1993-01-26 Motorola, Inc. Semiconductor device having an MOS transistor with overlapped and elevated source and drain
KR0144165B1 (ko) * 1995-05-12 1998-07-01 문정환 인버스 티(t)형 트랜지스터의 개선된 제조방법
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5960289A (en) * 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
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US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
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JP2009088134A (ja) * 2007-09-28 2009-04-23 Elpida Memory Inc 半導体装置、半導体装置の製造方法並びにデータ処理システム
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