CN107316837A - 一种cmos器件及其制造方法 - Google Patents
一种cmos器件及其制造方法 Download PDFInfo
- Publication number
- CN107316837A CN107316837A CN201710565796.9A CN201710565796A CN107316837A CN 107316837 A CN107316837 A CN 107316837A CN 201710565796 A CN201710565796 A CN 201710565796A CN 107316837 A CN107316837 A CN 107316837A
- Authority
- CN
- China
- Prior art keywords
- layer
- work
- channel region
- ion
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002070 nanowire Substances 0.000 claims description 11
- 229910004156 TaNx Inorganic materials 0.000 claims description 6
- 229910010421 TiNx Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052691 Erbium Inorganic materials 0.000 claims description 3
- 229910052693 Europium Inorganic materials 0.000 claims description 3
- 229910052779 Neodymium Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 34
- 230000008569 process Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- -1 metals nitride Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供一种CMOS器件的制造方法，包括：提供衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；在所述栅介质层上形成阻挡层；在所述阻挡层上形成功函数层；在所述功函数层上形成金属层；其中，在形成所述阻挡层之后，和/或形成所述功函数层之后，和/或形成所述金属层之后，还包括：进行等离子掺杂，等离子掺杂的离子为四族元素的离子。该方法调节阈值的控制精度高，且工艺灵活度高、简单易行，更适用于小尺寸器件中的多阈值的调控。
Description
技术领域
本发明涉及半导体器件及其制造领域，特别涉及一种CMOS器件及其制造方法。
背景技术
随着集成电路的集成度不断提高，器件的尺寸不断减小，传统的平面的CMOS(互补金属氧化物半导体)器件很难继续减小关键尺寸，立体器件，如FINFET(鳍式场效应晶体管)器件。
在进入纳米节点之后，CMOS器件的阈值电压的调节一直是器件制造中的重点和难点，目前，主要通过离子注入、栅宽(Gate Length)、栅介质层厚度以及功函数层来调节器件的阈值电压，而随着器件尺寸的进一步减小，尤其是进入10nm节点以下时，需要对多个阈值电压进行调节，而且由于尺寸减小带来的空间限制及寄生效应的影响，对阈值的调节提出了更高的要求，这些传统的方法已经不能很好地实现多阈值的调控。
发明内容
有鉴于此，本发明的目的在于提供一种CMOS器件及其制造方法，实现阈值电压的调节。
为实现上述目的，本发明有如下技术方案：
一种CMOS器件的制造方法，包括：
提供衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；
在所述栅介质层上形成阻挡层；
在所述阻挡层上形成功函数层；
在所述功函数层上形成金属层；
其中，在形成所述阻挡层之后，和/或形成所述功函数层之后，和/或形成所述金属层之后，还包括：进行等离子掺杂，等离子掺杂的离子为四族元素的离子。
可选地，所述沟道区域为鳍或纳米线。
可选地，所述阻挡层包括：TiN、TaN、TiNx、TaNx或TiNSi。
可选地，所述CMOS器件为NMOS，所述功函数层包括：Al、TiAl、TiAlx、TiAlCx、TiCx或TaCx。
可选地，所述CMOS器件为PMOS，所述功函数层包括：TiN、TaN、TiNx、TaNx或TiNSi。
可选地，所述金属层包括：Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er或La，或这些金属的合金以及这些金属的氮化物。
可选地，所述等离子掺杂的离子为Si4+、C+或Ge+。
一种CMOS器件，包括：
衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；
所述栅介质层上的阻挡层；
所述阻挡层上的功函数层；
所述功函数层上的金属层；
其中，在所述阻挡层和/或功函数层和/或金属层中具有等离子掺杂的离子，等离子掺杂的离子为四族元素的离子。
可选地，所述沟道区域为鳍或纳米线。
可选地，所述等离子掺杂的离子为Si4+、C+或Ge+。
本发明实施例提供的CMOS器件及其制造方法，在金属栅极工艺中，在形成阻挡层、功函数层或金属层中的任意一层或几层之后，通过等离子掺杂四族元素的离子，实现阈值电压的调节。该方法调节阈值的控制精度高，且工艺灵活度高、简单易行，更适用于小尺寸器件中的多阈值的调控。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本发明实施例的CMOS器件的制造方法的流程示意图；
图2示出了根据本发明实施例的COMS器件的制造方法中鳍的沟道区域的结构示意图；
图3示出了根据本发明实施例的COMS器件的制造方法中纳米线的沟道区域的结构示意图；
图4-图6示出了本发明实施例的CMOS器件的制造方法的制造过程中的截面结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本发明实施例提供了一种CMOS器件的制造方法，参考图1所示，所述制造方法包括：
步骤S101，提供衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；
步骤S102，在所述栅介质层上形成阻挡层；
步骤S103，在所述阻挡层上形成功函数层；
步骤S104，在所述功函数层上形成金属层；
其中，在形成所述阻挡层之后，和/或形成所述功函数层之后，和/或形成所述金属层之后，还包括：步骤S110，进行等离子掺杂，等离子掺杂的离子为四族元素的离子。
在本发明实施例的制造方法中，在形成金属栅极的过程中，在形成阻挡层、功函数层或金属层中的任意一层或几层之后，通过等离子掺杂四族元素的离子，实现阈值电压的调节。该方法调节阈值的控制精度高，且工艺简单易行，更适用于小尺寸器件中的多阈值的调控。
该方法尤其适用于小尺寸CMOS器件的功函数调节，例如10nm以下的CMOS器件，CMOS器件的结构可以为鳍式场效应晶体管或纳米线晶体管等，该方法可以应用于前栅工艺或后栅工艺中。
为了更好地理解本发明的技术方案和技术效果，以下将结合具体的实施例进行详细的说明。
参考图1所示，在步骤S101，提供衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层。
在本发明实施例中，所述衬底为半导体衬底，可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium On Insulator)等。在其他实施例中，所述半导体衬底还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
该衬底上已经具有沟道区域以及栅介质层，沟道区域为用于形成栅极结构的区域，在本发明实施例中，参考图2所示，沟道区域可以为鳍110，参考图3所示，沟道区域还可以为纳米线210，沟道区域还可以是其他任何的结构，可以采用合适的方法提供该沟道区域，本发明对沟道区域的结构和形成方法不作限定。
可以根据后续形成的栅极结构，来确定栅介质层的材料，在本发明实施例中，后续形成的栅极为金属栅极，栅介质层可以采用高k介质材料(例如，和氧化硅相比，具有高介电常数的材料)，高k介质材料例如铪基氧化物，HFO2、HfSiO、HfSiON、HfTaO、HfTiO等，此处仅为示例，本发明不限于此。栅介质层与沟道区域之间还可以形成有界面层，界面层用于改善界面特性，界面层可以为氧化硅或氮氧化硅等。
在一些实施例中，可以是应用于前栅工艺中，参考图2所示，首先，通过刻蚀衬底100形成鳍110的沟道区域，而后，淀积形成栅介质层112，之后，继续进行金属栅极的形成；在另一些工艺中，可以是应用于后栅工艺中，首先，参考图2所示，刻蚀衬底100形成鳍110的沟道区域，而后，形成栅介质层、伪栅极和源漏区(图未示出)，在去除伪栅极之后，继续进行金属栅极的形成。在另一些实施例中，还可以通过合适的方法形成纳米线的沟道区域，在一个具体的示例中，参考图3所示，可以通过刻蚀衬底200形成纳米线210，纳米线210的两端被支撑结构220支撑，其他区域被暴露出来，以用于形成全包围的栅极结构。以上形成沟道区域的方法仅为示例，本发明对此并不做限定。
在步骤S102，在所述栅介质层112上形成阻挡层114，参考图4所示。
所述阻挡层114用于防止金属向栅介质层以及沟道区域的扩散，所述阻挡层的材料可以选择以下中的一种或多种：TiN、TaN、TiNx、TaNx、TiNSi等。
可以通过CVD(化学气相沉积)、ALD(原子层沉积)或其他合适的淀积方法来形成该阻挡层。在一个具体的实施例中，可以采用ALD的方法形成TiN的阻挡层。
参考图4所示，在形成阻挡层114之后，可以进行等离子掺杂，等离子掺杂的离子为四族元素的离子，例如可以为Si4+、C+或Ge+等，等离子掺杂是指掺杂的离子为通过等离子处理之后获得的离子。这样，在等离子掺杂之后，阻挡层中掺杂有四族的离子，从而实现阈值电压的调节。
在步骤S103，在所述阻挡层114上形成功函数层116，参考图5所示。
所述功函数层116为用于器件进行功函数调节的膜层，对于NMOS器件，功函数层的材料可以从以下一种或多种选择：Al、TiAl、TiAlx、TiAlCx、TiCx、TaCx等。对于PMOS器件，功函数层的材料可以从以下一种或多种选择：TiN、TaN、TiNx、TaNx、TiNSi等。
可以通过CVD(化学气相沉积)、ALD(原子层沉积)或其他合适的淀积方法来形成该功函数层。在一个具体的实施例中，对于NMOS器件，可以采用ALD的方法形成TiAlC的功函数层，对于PMOS器件，可以采用CVD或ALD的方法形成TiN的功函数层。
同样地，在形成功函数层116之后，根据需要，也可以进一步进行等离子掺杂，等离子掺杂的离子为四族元素的离子，例如可以为Si4+、C+或Ge+等，等离子掺杂是指掺杂的离子为通过等离子处理之后获得的离子。这样，在等离子掺杂之后，功函数层中掺杂有四族的离子，通过工艺控制，在功函数层形成之后进行等离子掺杂，掺杂离子也可以进入到阻挡层中，从而，通过掺杂实现阈值电压的调节。
在步骤S104，在所述功函数层116上形成金属层118，参考图6所示。
所述金属层118为金属栅极的顶层金属，优选电阻率低的金属，在后栅工艺中，优选电阻率低且填充率高的金属，金属层的材料可以从以下一种或多种选择：Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er或La等，或这些金属的合金以及这些金属的氮化物。
可以通过溅射、ALD或CVD或其他合适的方法来形成填充层，在一个具体的实施例中，可以采用ALD的方法形成W的金属层。
同样地，在形成金属层118之后，根据需要，也可以进一步进行等离子掺杂，等离子掺杂的离子为四族元素的离子，例如可以为Si4+、C+或Ge+等，等离子掺杂是指掺杂的离子为通过等离子处理之后获得的离子。这样，在等离子掺杂之后，金属层中掺杂有四族的离子，通过工艺控制，在金属层形成之后进行等离子掺杂，掺杂离子也可以进入到功函数层，以及进一步进入到阻挡层中，从而，通过掺杂实现阈值电压的调节。
对于本发明的实施例，根据具体的需要，可以在阻挡层114、功函数层116或金属层118中的某一层或某几层中，通过掺杂来实现阈值电压的调节，这样，可以在形成阻挡层之后，和/或形成功函数层之后，和/或形成金属层之后，进行等离子掺杂，实现阈值电压的调节。
在10nm以下的器件中，对于NMOS和PMOS器件，典型地会有四种核心器件，也就是有四种阈值电压需要调节，这四种阈值电压分别为HVT、RVT、LVT、SLVT，若要实现分别的调控会增加额外的工艺步骤且难以实现，而在形成阻挡层，和/或功函数层，和/或金属层之后，进行等离子体掺杂，通过掺杂来实现功函数的调节，工艺灵活度高，控制精度高且简单易行。
此外，本发明还提供了上述实施例形成的CMOS器件，参考图6所示，包括：
衬底100，所述衬底100上具有沟道区域110以及沟道区域110上的栅介质层112；
所述栅介质层112上的阻挡层114；
所述阻挡层114上的功函数层116；
所述功函数层116上的金属层118；
其中，在所述阻挡层114和/或功函数层116和/或金属层118中具有等离子掺杂的离子，等离子掺杂的离子为四族元素的离子。
进一步地，所述等离子掺杂的离子为Si4+、C+或Ge+。
进一步地，所述沟道区域110为鳍或纳米线。
以上所述仅是本发明的优选实施方式，虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。
Claims (10)
1.一种CMOS器件的制造方法，其特征在于，包括：
提供衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；
在所述栅介质层上形成阻挡层；
在所述阻挡层上形成功函数层；
在所述功函数层上形成金属层；
其中，在形成所述阻挡层之后，和/或形成所述功函数层之后，和/或形成所述金属层之后，还包括：进行等离子掺杂，等离子掺杂的离子为四族元素的离子。
2.根据权利要求1所述的制造方法，其特征在于，所述沟道区域为鳍或纳米线。
3.根据权利要求1所述的制造方法，其特征在于，所述阻挡层包括：TiN、TaN、TiNx、TaNx或TiNSi。
4.根据权利要求1所述的制造方法，其特征在于，所述CMOS器件为NMOS，所述功函数层包括：Al、TiAl、TiAlx、TiAlCx、TiCx或TaCx。
5.根据权利要求1所述的制造方法，其特征在于，所述CMOS器件为PMOS，所述功函数层包括：TiN、TaN、TiNx、TaNx或TiNSi。
6.根据权利要求1所述的制造方法，其特征在于，所述金属层包括：Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er或La，或这些金属的合金以及这些金属的氮化物。
7.根据权利要求1-6中任一项所述的制造方法，其特征在于，所述等离子掺杂的离子为Si4+、C+或Ge+。
8.一种CMOS器件，其特征在于，包括：
衬底，所述衬底上具有沟道区域以及沟道区域上的栅介质层；
所述栅介质层上的阻挡层；
所述阻挡层上的功函数层；
所述功函数层上的金属层；
其中，在所述阻挡层和/或功函数层和/或金属层中具有等离子掺杂的离子，等离子掺杂的离子为四族元素的离子。
9.根据权利要求8所述的器件，其特征在于，所述沟道区域为鳍或纳米线。
10.根据权利要求8或9所述的器件，其特征在于，所述等离子掺杂的离子为Si4+、C+或Ge+。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710565796.9A CN107316837A (zh) | 2017-07-12 | 2017-07-12 | 一种cmos器件及其制造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710565796.9A CN107316837A (zh) | 2017-07-12 | 2017-07-12 | 一种cmos器件及其制造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107316837A true CN107316837A (zh) | 2017-11-03 |
Family
ID=60178675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710565796.9A Pending CN107316837A (zh) | 2017-07-12 | 2017-07-12 | 一种cmos器件及其制造方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107316837A (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019116152A1 (en) * | 2017-12-15 | 2019-06-20 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842491A (zh) * | 2011-06-24 | 2012-12-26 | 联华电子股份有限公司 | 金属栅极的制作方法 |
| US20130241003A1 (en) * | 2012-03-13 | 2013-09-19 | Chien-Ting Lin | Finfet and fabricating method thereof |
| CN104347411A (zh) * | 2013-08-01 | 2015-02-11 | 中国科学院微电子研究所 | 金属栅电极等效功函数调节方法 |
| CN105428361A (zh) * | 2014-09-19 | 2016-03-23 | 中国科学院微电子研究所 | Cmos器件及其制造方法 |
| CN105826265A (zh) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
-
2017
- 2017-07-12 CN CN201710565796.9A patent/CN107316837A/zh active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842491A (zh) * | 2011-06-24 | 2012-12-26 | 联华电子股份有限公司 | 金属栅极的制作方法 |
| US20130241003A1 (en) * | 2012-03-13 | 2013-09-19 | Chien-Ting Lin | Finfet and fabricating method thereof |
| CN104347411A (zh) * | 2013-08-01 | 2015-02-11 | 中国科学院微电子研究所 | 金属栅电极等效功函数调节方法 |
| CN105428361A (zh) * | 2014-09-19 | 2016-03-23 | 中国科学院微电子研究所 | Cmos器件及其制造方法 |
| CN105826265A (zh) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019116152A1 (en) * | 2017-12-15 | 2019-06-20 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| US10685886B2 (en) | 2017-12-15 | 2020-06-16 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| CN111433905A (zh) * | 2017-12-15 | 2020-07-17 | 国际商业机器公司 | 在同一个衬底上制造逻辑器件和功率器件 |
| GB2582087A (en) * | 2017-12-15 | 2020-09-09 | Ibm | Fabrication of logic devices and power devices on the same substrate |
| US11244869B2 (en) | 2017-12-15 | 2022-02-08 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| GB2582087B (en) * | 2017-12-15 | 2022-03-30 | Ibm | Fabrication of logic devices and power devices on the same substrate |
| CN111433905B (zh) * | 2017-12-15 | 2023-12-22 | 国际商业机器公司 | 在同一个衬底上制造逻辑器件和功率器件 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9685441B2 (en) | Semiconductor device with tunable work function | |
| TWI536544B (zh) | 形成具有多重功函數閘極結構之方法及所產生之產品 | |
| TWI476823B (zh) | 半導體裝置與具有金屬閘極之半導體裝置的製造方法 | |
| US8404594B2 (en) | Reverse ALD | |
| US8410555B2 (en) | CMOSFET device with controlled threshold voltage and method of fabricating the same | |
| CN102299156B (zh) | 一种半导体器件及其制造方法 | |
| JP5781944B2 (ja) | スレッショルド調節半導体合金を堆積させるのに先立ちパターニング不均一性を低減することによる前記半導体合金の厚みばらつきの低減 | |
| CN102110650A (zh) | 一种半导体器件及其制造方法 | |
| CN102969347A (zh) | 提供具有多阻挡层的金属栅极器件的技术 | |
| US9269804B2 (en) | Gate recessed FDSOI transistor with sandwich of active and etch control layers | |
| US20130087856A1 (en) | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate | |
| JP2010525591A (ja) | 高ｋゲート誘電体を有するＣＭＯＳ回路 | |
| US20180175029A1 (en) | Integrated Circuit With A Gate Structure And Method Making The Same | |
| WO2013000268A1 (zh) | 一种半导体结构及其制造方法 | |
| JP5669752B2 (ja) | チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 | |
| JP2010177240A (ja) | 半導体装置及びその製造方法 | |
| CN104347411A (zh) | 金属栅电极等效功函数调节方法 | |
| CN102110689A (zh) | 一种半导体器件及其制造方法 | |
| US7098516B2 (en) | Refractory metal-based electrodes for work function setting in semiconductor devices | |
| CN109216177A (zh) | 栅极结构及其方法 | |
| CN106298665B (zh) | 半导体器件的制造方法 | |
| CN107316837A (zh) | 一种cmos器件及其制造方法 | |
| CN106328501B (zh) | 半导体器件的制造方法 | |
| CN107464783B (zh) | 一种cmos器件及其制作方法 | |
| CN103531540A (zh) | 半导体器件制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171103 |
|
| RJ01 | Rejection of invention patent application after publication |