TWI476823B - 半導體裝置與具有金屬閘極之半導體裝置的製造方法 - Google Patents

半導體裝置與具有金屬閘極之半導體裝置的製造方法 Download PDF

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TWI476823B
TWI476823B TW101111999A TW101111999A TWI476823B TW I476823 B TWI476823 B TW I476823B TW 101111999 A TW101111999 A TW 101111999A TW 101111999 A TW101111999 A TW 101111999A TW I476823 B TWI476823 B TW I476823B
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semiconductor device
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Jeff J Xu
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Description

半導體裝置與具有金屬閘極之半導體裝置的製造方法
本發明係有關於半導體裝置,且特別是有關於一種具有高介電常數材料/金屬閘極之半導體裝置及其製造方法。
當例如金氧半場效電晶體(MOSFET)之半導體裝置微縮至各種技術節點時,已有許多技術用以增進裝置效能。其中一種技術係為使用高介電常數介電材料及金屬閘極電晶體。另一種技術則為使用應變基材(strained substrate)。例如,如使用應變基材技術,可藉由調整電晶體通道中之應變來改善遷移率(例如電子或電洞遷移率),並因而改善通道之導電性及使裝置具有較佳的效能。例如,鍺化矽磊晶層或碳化矽磊晶層,係各自形成於P型場效電晶體中之源極/汲極區及N型場效電晶體中之源極/汲極區中。然而,目前用以形成上述應變結構之技術無法滿足各方面的需求。例如,這些應變結構可能無法在通道區中產生足夠的應力來改善裝置效能。
本發明實施例係提供一種具有金屬閘極之半導體裝置,包括:一半導體基材,包含複數個源極及汲極元件以形成一p型通道及一n型通道;以及一閘極堆疊設置於此半導體基材上及位於這些源極及汲極元件之間,其中此閘極堆疊包含:一高介電常數介電層形成於此半導體基材上;一拉伸應力高介電常數蓋層形成於此高介電常數介電層之頂部上,並鄰近於此p型通道;一壓縮應力高介電常數n型功函數金屬層形成於此高介電常數介電層之頂部上,並鄰近於此n型通道;以及一金屬閘極層之堆疊沉積於這些蓋層上。
本發明實施例亦提供一種具有金屬閘極之半導體裝置之製造方法,包括:提供一半導體基材;形成隔離的NMOS區域及PMOS區域於此半導體基材中;沉積一高介電常數介電層於此半導體基材上;沉積一拉伸應力高介電常數蓋層於位於此NMOS區域及此PMOS區域中之此高介電常數介電層之頂部上;自此NMOS區域中移除此拉伸應力高介電常數蓋層;沉積一壓縮應力N型功函數金屬層於此NMOS區域及此PMOS區域中之此高介電常數介電層上;以及沉積一金屬閘極層之堆疊於此壓縮應力N型功函數金屬層上。
本發明實施例更提供一種具有金屬閘極之半導體裝置,包括:一半導體基材;一界面層形成於此半導體基材上;一高介電常數介電層形成於此半導體基材上;一拉伸應力高介電常數蓋層形成於此半導體基材之一PMOS區域中之此界面層上;一壓縮應力高介電常數蓋層形成於此半導體基材之一NMOS區域中之此界面層上;一金屬閘極堆疊沉積於這些高介電常數蓋層上;其中此NMOS區域中及此PMOS區域中之這些高介電常數蓋層係為兩種不同的應力類型;其中此NMOS區域中及此PMOS區域中的通道係為兩種不同種類的應變通道。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。值得注意的是,這些實施例提供許多可行之發明概念並可實施於各種特定情況。然而,在此所討論之這些特定實施例僅用於舉例說明本發明之製造及使用方法,但非用於限定本發明之範圍。再者,當在本說明書中提及第一製程在第二製程之前進行時,第二製程可為在第一製程之進行後隨即進行,或可有其他額外的製程插在第一製程及第二製程之間進行。各種元件可能以任意不同比例顯示以使圖示清晰簡潔。此外,當在本說明書中提及第一元件位於第二元件上方時,可能包含第一元件及第二元件直接接觸,或中間更插有其他元件使得第一元件及第二元件未直接接觸。
第1圖顯示依照本發明一實施例之以後閘極製程製造具有高介電常數材料/金屬閘極之半導體裝置之方法100之流程圖。以下,方法100係配合第2至7圖作說明。在後閘極製程(或閘極替換製程)中,首先形成虛置(犧牲)多晶矽閘極結構,並接著進行普通的CMOS製程,直至沉積層間介電層。接著,可移除虛置多晶矽閘極結構,並以金屬閘極將其替換。因此,閘極係在進行高溫製程之後形成,例如在形成源極/汲極區之後形成。後閘極製程(或閘極替換製程)可避免功函數材料因高溫製程而穩定性不佳的問題。
方法100起始於步驟102,首先提供半導體基材210。在本實施例中,基材210包含矽。或者,基材可包含鍺、鍺化矽或其他合適半導體材料。或者,半導體基材210可包含磊晶層。例如,基材210可具有一磊晶層覆於塊狀半導體上。此外,基材210可為應變以增進效能。例如,磊晶層可包含不同於半導體塊材之半導體材料,例如由選擇性磊晶成長所形成之矽塊材上覆鍺化矽層或鍺化矽塊材上覆矽層。此外,基材210可包含絕緣體上覆半導體(SOI)結構,例如埋藏介電層。或者,基材可包含埋藏介電層,例如埋藏氧化層,其可由例如佈植氧加以分離(separation by implantation of oxygen,SIMOX)、晶圓接合、選擇性磊晶成長或其他合適方法形成。事實上,在各實施例中可包含任意之合適基材結構及材料。
在第2圖中,基材210亦包含各種隔離元件,且這些隔離元件可包含使用不同製程技術所形成之不同結構。例如,隔離元件可包含淺溝槽隔離元件220。淺溝槽隔離元件之形成步驟可包含在基材210中蝕刻出溝槽(未顯示),並以例如氧化矽、氮化矽或氮氧化矽之絕緣材料填滿此溝槽。此填滿之溝槽可具有多層結構,例如以熱氧化襯層內襯於溝槽中並以氮化矽填滿溝槽。例如,可使用如下之製程順序形成淺溝槽隔離結構:成長氧化物墊層;以低壓化學氣相沉積形成氮化物層;使用光阻及罩幕圖案化出淺溝槽隔離開口;在基材中蝕刻出溝槽;以化學氣相沉積氧化物填滿開口;使用化學機械平坦化(CMP)製程回蝕刻過剩的氧化物。
繼續參見第2圖,以佈植技術形成各種摻雜元件,例如P型井230及N型井235。部分的基材210具有P型摻雜而形成P型井230。隨後,n型通道裝置將形成於此P型井230中。類似地,部分的基材210具有N型摻雜而形成N型井235。隨後,p型通道裝置將形成於此N型井235中。例如,基材210可包含各種摻雜P型摻質(例如硼或二氟化硼)、N型摻質(例如磷或砷)或前述之組合之各種摻雜區域。摻雜區域可形成於半導體基材上、P型井區結構中、N型井區結構中或雙井區結構中。或者,可使用隆起結構作為摻雜區域。
層間介電層可由臭氧氧化法、化學氣相沉積、原子層沉積或其他合適方法形成。層間介電層可例如為二氧化矽。隨後,以沉積技術形成閘極材料(例如多晶矽)於層間介電層上。例如,可在化學氣相沉積製程中,使用矽烷(silane)、乙矽烷(di-silane)或二氯乙矽烷(SiCl2 H4 )作為化學氣體,以形成多晶矽層。或者,可選擇性地形成非晶矽層來取代多晶矽層。既然多晶矽層可於隨後被金屬閘極電極所取代,多晶矽層可稱為虛置多晶矽層。界面介電層及虛置閘極層係經圖案化,以形成虛置閘極堆疊(未顯示)。
繼續參見第2圖,以例如一或多個離子佈植步驟之合適製程形成源極及汲極區250、251。源極及汲極區250及251可更包含實質上對齊於虛置閘極堆疊之輕摻雜源極/汲極(LDD)區及實質上對齊於閘極側壁間隔物260之重摻雜源極及汲極區250、251。
繼續參見第2圖,側壁間隔物260係形成於虛置閘極結構之側壁上。側壁間隔物260可包含介電材料,例如氧化矽。或者,側壁間隔物260可選擇性地包含氮化矽、碳化矽、氮氧化矽或前述之組合。閘極側壁物260係由介電沉積(dielectric deposition)及乾蝕刻製程形成。在形成閘極側壁物260之後,可使用磊晶成長製程來創造磊晶成長區270。例如,可使用蝕刻製程以在基材210中形成凹陷,並使用磊晶成長來形成磊晶成長區270。在P型場效電晶體(PFET)裝置中,磊晶成長區270可包含鍺化矽(SiGe)。然而,在其他不同之實施例中,磊晶成長區270可為其他合適材料。
在形成源極及汲極區域250、251之後,可進行一或多道退火製程活化源極及汲極區。退火製程包含快速熱退火、雷射退火或其他合適退火製程。例如,高溫熱退火步驟可為施予900℃至1100℃之間的任意溫度,且在其他實施例中亦可施予不同的溫度。在另一實施例中,高溫退火製程包含超過600℃之高溫處理。再者,本實施例可包含週期極短的“瞬間(spike)”退火製程。
繼續參見第2圖,形成層間介電層於半導體基材210及虛置閘極上。可進行化學機械研磨製程以移除層間介電層280,暴露出虛置閘極。或者,可額外形成硬罩幕於虛置閘極之頂部上。例如,進行化學機械研磨直至暴露出硬罩幕,再以例如濕式浸泡蝕刻之蝕刻製程移除硬罩幕層,以暴露出虛置閘極。接著,再以蝕刻製程移除N型場效電晶體(NFET)及P型場效電晶體(PFET)中的虛置閘極,以在NFET及PFET區域中形成閘極溝槽282。虛置閘極可由乾蝕刻、濕蝕刻或前述之組合予以移除。例如,濕蝕刻可包含暴露在含氫氧化物之溶液中(例如氫氧化銨)、去離子水及或其他合適蝕刻溶液,在某些實施例中,亦可在移除虛置閘極後,使用例如氫氟酸濕蝕刻或其他合適製程移除界面層,以暴露出基材表面。
接著,繼續進行方法100之步驟104,如第3圖所示,沉積界面層285及高介電常數介電層290於閘極溝槽282上。界面層285可包含氧化矽(SiO2 )層(例如以熱氧化或化學氧化法形成)。或者,界面層285可選擇性地包含由原子層沉積、化學氣相沉積、物理氣相沉積、熱氧化法或前述方法組合所形成之氧化鉿矽(HfSiO)或氮氧化矽。已觀察到的是,界面層可提供修復某些高介電常數介電閘極堆疊整合的問題,例如臨界電壓釘札(threshold voltage pinning)及載子遷移率降低等問題。由於閘極介電層在電晶體通道上的影響及電性效能係為各膜層之各別影響之總和,可針對各類的電晶體應用來由調整界面層厚度,以控制臨界電壓。界面層可與擴散阻障層具有相同功能,防止高介電常數介電材料與基材之間產生不欲的界面反應。高介電常數介電層290可由原子層沉積、化學氣相沉積、有機金屬化學氣相沉積(metaloragnic CVD,MOCVD)、熱氧化法、前述之組合或其他合適技術形成。
高介電常數介電層290可包含二元或三元高介電常數膜層,例如氧化鉿(HfOx )。或者,高介電常數介電層290可選擇性地包含其他高介電常數介電材料,例如氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、五氧化二鉭(Ta2 O5 )、三氧化二釔(Y2 O3 )、鈦酸鍶(SrTiO3 ,STO)、鈦酸鋇(BaTiO3 ,BTO)、鋯酸鋇(BaZrO3 )、鋯酸鉿(HfZrO3 )、氧化鉿鑭(HfLaO)、氧化鉿矽(HfSiO)、鑭矽氧化物(LaSiO)、矽鋁氧化物(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、鈦酸鋇鍶((Ba,Sr)TiO3 ,BST)、三氧化二鋁(Al2 O3 )、氮化矽(Si3 N4 )、氮氧化物(oxynitrides)或其他合適材料。在所述之實施例中,高介電常數介電層290可包含由原子層沉積形成之氧化鉿(HfO2 )。此外,可在沉積高介電常數介電層後進行退火,以增進對閘極介電層的濕度控制。
接著,進行方法100之步驟106,如第4圖所示,沉積蓋層300於高介電常數介電層290上。蓋層300可導電並防止高介電常數介電層290與金屬閘極層之間的相互擴散及反應。適於形成高介電常數蓋層之材料可包含難熔金屬(refractory metal)及其氮化物,例如氮化鈦、氮化鉭、氮化鎢(W2 N)、氮化鈦矽(TiSiN)、氮化鉭矽(TaSiN)。高介電常數蓋層可由物理氣相沉積、化學氣相沉積、有機金屬化學氣相沉積(MOCVD)或原子層沉積形成。物理氣相沉積係為一包含在表面上進行物理處理(例如電漿濺鍍轟擊,plasma sputter bombardment)但不包含化學反應之沉積方法。在電漿濺鍍處理製程中,以高能粒子轟擊標靶材料而從其中放出原子或分子,以使所放出的原子或分子能凝聚在基材上形成一薄膜。原子層沉積係為一氣相化學製程,且自限制之原子層及原子層堆疊成長之方法。原子層沉積的表面控制成長機制提供其具有良好的階梯覆蓋率及緻密的膜層(沒有或僅具有稀少的小孔)。依照原子層沉積所具有的精確度,使其可在經控制的情況下沉積奈米尺度下之極薄膜層。
當所形成之高介電常數蓋層鄰近PFET及NFET之通道區時,高介電常數蓋層之膜層應力(壓縮或拉伸)可導致通道的應變(strained)。例如,拉伸應力高介電常數蓋層可導致鄰近的p型通道具有壓縮應變。壓縮應力高介電常數蓋層可導致鄰近的n型通道具有拉伸應變。已觀察到的是,當具有所欲型態之通道應變時,可增進載子遷移率及裝置效能。例如,p型通道壓縮應變可增進電洞遷移率,n型通道拉伸應變可增進電子遷移率。高介電常數蓋層之應力型態及強度可由高介電常數蓋層之沉積方法、沉積條件及材料所控制。在一實施例中,由原子層沉積所形成之氮化鈦層可具有拉伸應力。在另一實施例中,由物理氣相沉積所形成之氮化鈦層可依照沉積條件而具有拉伸應力或壓縮應力,例如控制沉積溫度。在所述之實施例中,高介電常數蓋層300包含由原子層沉積形成之氮化鈦,其具有拉伸應力。同時,由原子層沉積形成之氮化鈦高介電常數蓋層300可作為PMOS之P型功函數金屬層。
目前已知的是,不同型態之應變對PMOS及NMOS具有不同的效果。例如,施予壓縮應變至通道時,可增進PMOS之效能,反之,施予拉伸應變至通道時,可增進NMOS之效能。因此,藉由導入局部的應變,將可獨立地調控n型通道及p型通道的應變。
接著,進行方法100之步驟108,如第5圖所示,移除位在NFET區中之部分的高介電常數蓋層300。位在NFET中的高介電常數蓋層300可藉由圖案化及蝕刻技術予以移除。移除技術可包含乾蝕刻、濕蝕刻或前述之組合。在所述之實施例中,可自NMOS部分中移除拉伸應力蓋層300,以打開NMOS的部分而在隨後於鄰近n型通道之區域接受不同應力型態之蓋層。因此,可在不受p型通道影響下,獨立地調控n型通道之應變。此外,在所述之實施例中,自NMOS部分移除由由原子層沉積形成之氮化鈦蓋層300(具有中等能隙之功函數金屬),可增進對NMOS臨界電壓之控制。
接著,繼續進行方法100之步驟110,如第6圖所示。沉積N型功函數金屬層310於NMOS及PMOS上。由於已打開NMOS的部分,N型功函數金屬層310鄰近於n型通道。因此,壓縮應力N型功函數金屬層310可產生拉伸應力至n型通道,其可增進電子遷移率。N型功函數金屬層310可包含單一金屬層或多層金屬層結構,例如鈦、錳、鋯、氮化鉭、氮化鈦、鋁化鈦、氮化鈦鋁(TiAlN1-x )、碳化鉭、氮化鉭碳(TaCN)、氮化鉭矽(TaSiN)或前述之組合。N型功函數金屬層310可由原子層沉積、物理氣相沉積、化學氣相沉積或其他合適製程形成。
N型功函數金屬層310之應力型態及應力強度可由N型功函數金屬層310之沉積方法、沉積條件及材料決定。在所述之實施例中,N型功函數金屬層310包含由物理氣相沉積形成之氮化鈦鋁(TiAlN1-x )層,其具有壓縮應力。此外,在一實施例中,可在N型功函數金屬層310作為NMOS之高介電常數蓋層之前額外地沉積由物理氣相沉積形成之氮化鈦鋁層(未顯示),以增進裝置之可靠度,例如改善正向偏壓溫度不穩定性(positive bias temperature instability,PBTI)。
繼續參見第6圖,在所述之實施例中,氮化鈦鋁功函數層310沉積在NMOS及PMOS上。已觀察到的是,氮化鈦鋁(TiAlN1-x )可較於鋁化鈦(TiAl)具有更佳的熱穩定性,其可同時使NMOS裝置及PMOS裝置增進其臨界電壓之穩定性。此外,N型功函數金屬層310鄰近在NMOS中的高介電常數介電層290的頂部,可扮演在NMOS中之高介電常數介電層290之蓋層之一。藉由使用較為穩定之功函數金屬層,例如氮化鈦鋁(TiAlN1-x ),可改善高介電常數介電層之時間相依介電崩潰(time-dependent-dielectric-breakdown,TDDB)可靠度問題,且在經驗上亦可使NMOS及PMOS之臨界電壓更為穩定。
接著,繼續進行步驟112,在NMOS中形成N型金屬閘極堆疊350A於N型功函數金屬層310上,及在PMOS中形成P型金屬閘極堆疊350B於N型功函數金屬層310上。金屬閘極堆疊350A及350B可同時或各自獨立形成。金屬閘極堆疊350A及350B可包含功函數層(例如300及310)、填充金屬層、襯層、潤濕層及黏著層。再者,金屬閘極堆疊350A可包含單一金屬層或多層金屬層結構,以具有足夠低的有效功函數值,例如包含鈦、銀、鋁、氮化鈦鋁(TiAlN)、碳化鉭(TaC)、氮化鉭碳(TaCN)、氮化鉭矽(TaSiN)、錳、鋯或前述之組合。
P型金屬閘極堆疊350B可包含單一金屬層或多層金屬層結構,以具有足夠高的有效功函數值,例如氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢或前述之組合。金屬閘極堆疊350A及350B可由原子層沉積、物理氣相沉積、化學氣相沉積、或其他合適製程形成。在一實施例中,可先沉積鈦層作為潤濕層,以利於隨後鋁層之沉積。鈦層可由物理氣相沉積或其他合適方法形成。在另一實施例中,填充金屬可包含鋁及由物理氣相沉積、化學氣相沉積或其他合適技術。或者,填充金屬層可包含銅及鎢。
在所述之實施例中,金屬閘極堆疊350A及350B可包含由物理氣相沉積形成之鈦潤濕層及由物理氣相沉積之鋁填充金屬層。在一實施例中,阻障層可形成於鋁填充金屬層之下。阻障層可包含由物理氣相沉積形成之氮化鈦。阻障層之擴散阻障性質可隨著材料之化學計量(stoichiometry)及沉積方法作任意變換。擴散阻障性質將影響裝置之效能。例如,富氮之氮化鈦阻障層(氮比鈦之比例大於1)對於鋁金屬層之防止鋁擴散至進入高電常數介電層的效果極為有效,如產生這些擴散將會對裝置的可靠度造成影響,例如時間相依介電崩潰。富氮之氮化鈦通常較富鈦之氮化鈦(鈦比氮的比例大於1)具有較佳的熱穩定性。或者,在其他實施例中,阻障層可包含由任意組成成分(例如三種或更多種)之組成之膜層,且可為任意數量的膜層組成。在一實施例中,藉由使用化學沉積製程或其他製程沉積金屬層。藉由上述之方法,可由不同的組成成分及組態來形成NMOS及PMOS金屬閘極堆疊。NMOS及PMOS金屬閘極堆疊之功函數可各自獨立地調控。
接著,進行進行方法100之步驟112,在一實施例中,由原子層沉積形成之氮化鉭層形成於高介電常數蓋層之頂部上,作為虛置閘極結構中之蝕刻停止層。已觀察到的是,氮化鉭蝕刻停止層可使NMOS之臨界電壓朝向不欲之上升。在移除虛置閘極後,可將此氮化鉭蝕刻停止層移除以增進NMOS臨界電壓之穩定性。
可在各種金屬層上進行化學機械研磨以將NMOS及PMOS裝置平坦化。化學機械研磨製程對金屬層及介電層280可具有高度的選擇性。化學機械研磨製程可提供金屬閘極堆疊350A、350B及層間介電層240實質上平坦之表面,如第7圖所示。
方法100可更包含形成多層內連線。多層內連線結構可包含垂直內連線(例如傳統的通孔或接觸點)及水平內連線(例如金屬線)。各種內連線元件可使用各種各種導電材料,包含銅、鎢及矽化物。在一實施例中,可使用鑲嵌製程以形成銅相關的多層內連線結構。在另一實施例中,可使用鎢在接觸孔中形成鎢插塞。
雖然本發明已以數個較佳實施例揭露如上以使本發明之概念易於明瞭,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,當可依本發明為基礎作設計及修改製程或結構,以實現相同目的及/或達成本發明揭露之實施例之相同技術效果。任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
210...基材
220...淺溝槽隔離元件
230...P型井
235...N型井
250...源極/汲極區
251...源極/汲極區
260...側壁間隔物
270...磊晶成長區
280...層間介電層
282...閘極溝槽
285...界面層
290...高介電常數介電層
300...高介電常數蓋層
310...N型功函數金屬層
350A...金屬閘極堆疊
350B...金屬閘極堆疊
第1圖顯示依照本發明一實施例之以後閘極製程製造具有高介電常數材料/金屬閘極之半導體裝置之流程圖。
第2至7圖顯示依照本發明一實施例之以後閘極製程製造具有高介電常數材料/金屬閘極之半導體裝置於各種中間製程之剖面圖。
210‧‧‧基材
220‧‧‧淺溝槽隔離元件
230‧‧‧P型井
235‧‧‧N型井
250‧‧‧源極/汲極區
251‧‧‧源極/汲極區
260‧‧‧側壁間隔物
270‧‧‧磊晶成長區
280‧‧‧層間介電層
285‧‧‧界面層
290‧‧‧高介電常數介電層
300‧‧‧高介電常數蓋層
310‧‧‧N型功函數金屬層
350A‧‧‧金屬閘極堆疊
350B‧‧‧金屬閘極堆疊

Claims (9)

  1. 一種半導體裝置,包括:一半導體基材,包含一p型通道夾設於一第一源極區與一第一汲極區之間,以及一n型通道夾設於一第二源極區與一第二汲極區之間;一第一閘極堆疊設置於該半導體基材上及位於該p型通道區上,其中該第一閘極堆疊包含:一高介電常數介電層形成於該半導體基材上;一拉伸應力高介電常數蓋層形成於該高介電常數介電層之頂部上,並位於該p型通道上;一第二閘極堆疊位於該半導體基材上及位於該n型通道區上,其中該第二閘極堆疊包含:該高介電常數介電層;以及一壓縮應力n型功函數金屬層形成於該高介電常數介電層之頂部上,並位於該n型通道上。
  2. 如申請專利範圍第1項所述之半導體裝置,其中該拉伸應力高介電常數蓋層包含一由原子層沉積形成之氮化鈦層,且其中該p型通道係為一壓縮應變通道。
  3. 如申請專利範圍第1項所述之半導體裝置,其中該壓縮應力N型功函數金屬層包含一由物理氮相沉積形成之氮化鈦鋁層,且其中該n型通道係為一拉伸應變通道。
  4. 一種具有金屬閘極之半導體裝置之製造方法,包括:提供一半導體基材,其具有一NMOS區域及一PMOS區域; 沉積一高介電常數介電層於該半導體基材上;沉積一拉伸應力高介電常數蓋層於位於該NMOS區域及該PMOS區域中之該高介電常數介電層之頂部上;自該NMOS區域中移除該拉伸應力高介電常數蓋層;沉積一壓縮應力N型功函數金屬層於該NMOS區域及該PMOS區域中之該高介電常數介電層上,其中該N型功函數金屬層位於該PMOS區域中的該拉伸應力高介電常數蓋層上;以及沉積一金屬閘極層之堆疊於該壓縮應力N型功函數金屬層上。
  5. 如申請專利範圍第4項所述之具有金屬閘極之半導體裝置之製造方法,其中沉積該拉伸應力高介電常數蓋層之步驟包含以原子層沉積法沉積一氮化鈦層。
  6. 如申請專利範圍第4項所述之具有金屬閘極之半導體裝置之製造方法,其中該壓縮應力N型功函數金屬層包含一由物理氣相沉積形成之氮化鈦鋁層。
  7. 如申請專利範圍第4項所述之具有金屬閘極之半導體裝置之製造方法,更包含:形成一虛置閘極於該半導體基材上;沉積一層間介電層於該半導體基材上;移除該虛置閘極以形成一閘極溝槽;其中該高介電常數介電層係沉積於該閘極溝槽中。
  8. 一種具有金屬閘極之半導體裝置,包括:一PMOS閘極結構,包括: 一高介電常數介電層形成於該半導體基材上;氮化鈦之一拉伸應力高介電常數層直接形成於該高介電常數介電層上;一壓縮應力層;以及多個金屬層形成於該拉伸應力高介電常數介電層上;一NMOS閘極結構,包括該高介電常數介電層形成於該半導體基材上;該壓縮應力層形成於該高介電常數介電層上;多個金屬閘極層沉積於該壓縮應力層上。
  9. 如申請專利範圍第8項所述之具有金屬閘極之半導體裝置,其中氮化鈦的該拉伸應力高介電常數層由原子層沉積法形成,該壓縮應力包含一由物理氣相沉積法形成之氮化鈦層,其中氮化鈦的該拉伸應力高介電常數層下的該p型通道係為一壓縮應變通道,該壓縮應力層下的該n型通道係為一拉伸應變通道。
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