JPWO2023149131A5 - - Google Patents

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JPWO2023149131A5
JPWO2023149131A5 JP2023578422A JP2023578422A JPWO2023149131A5 JP WO2023149131 A5 JPWO2023149131 A5 JP WO2023149131A5 JP 2023578422 A JP2023578422 A JP 2023578422A JP 2023578422 A JP2023578422 A JP 2023578422A JP WO2023149131 A5 JPWO2023149131 A5 JP WO2023149131A5
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semiconductor region
depth position
impurity concentration
main surface
semiconductor
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JP2023578422A
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JPWO2023149131A1 (https=
JP7750312B2 (ja
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Priority claimed from PCT/JP2022/047790 external-priority patent/WO2023149131A1/ja
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JP2023578422A 2022-02-02 2022-12-23 半導体装置および半導体装置の製造方法 Active JP7750312B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022015237 2022-02-02
JP2022015237 2022-02-02
PCT/JP2022/047790 WO2023149131A1 (ja) 2022-02-02 2022-12-23 半導体装置および半導体装置の製造方法

Publications (3)

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JPWO2023149131A1 JPWO2023149131A1 (https=) 2023-08-10
JPWO2023149131A5 true JPWO2023149131A5 (https=) 2024-04-24
JP7750312B2 JP7750312B2 (ja) 2025-10-07

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JP2023578422A Active JP7750312B2 (ja) 2022-02-02 2022-12-23 半導体装置および半導体装置の製造方法

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US (1) US20240213307A1 (https=)
JP (1) JP7750312B2 (https=)
CN (1) CN117716514A (https=)
WO (1) WO2023149131A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6981890B2 (ja) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6115678B1 (ja) * 2016-02-01 2017-04-19 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
DE102018123164B3 (de) * 2018-09-20 2020-01-23 Infineon Technologies Ag Halbleitervorrichtung, die eine graben-gatestruktur enthält, und herstellungsverfahren
JP7290028B2 (ja) * 2019-01-21 2023-06-13 富士電機株式会社 半導体装置および半導体装置の製造方法
JP7570168B2 (ja) * 2019-06-14 2024-10-21 富士電機株式会社 炭化珪素半導体装置

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