JP2020150179A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2020150179A JP2020150179A JP2019047712A JP2019047712A JP2020150179A JP 2020150179 A JP2020150179 A JP 2020150179A JP 2019047712 A JP2019047712 A JP 2019047712A JP 2019047712 A JP2019047712 A JP 2019047712A JP 2020150179 A JP2020150179 A JP 2020150179A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- region
- pad
- polysilicon layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 188
- 239000010410 layer Substances 0.000 claims abstract description 174
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 155
- 229920005591 polysilicon Polymers 0.000 claims abstract description 153
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 239000011229 interlayer Substances 0.000 claims abstract description 49
- 239000010408 film Substances 0.000 claims description 149
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 38
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 16
- 230000002829 reductive effect Effects 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置60を半導体基板(半導体チップ)のおもて面側から見たレイアウトを示す平面図である。図2は、図1の一部を拡大して示す平面図である。図2には、図1のゲートパッド2の周辺を示す。まず、実施の形態1にかかる半導体装置60を半導体基板のおもて面側から見たレイアウトについて説明する。
次に、実施の形態2にかかる半導体装置の構造について説明する。図6は、実施の形態2にかかる半導体装置の一部を半導体基板のおもて面側から見たレイアウトを示す平面図である。図7は、図6の切断線B−B’における断面構造を示す断面図である。実施の形態2にかかる半導体装置60の全体を半導体基板10のおもて面側から見たレイアウトは、図1のゲートポリシリコン層3の第1部分3aを、図6のゲートポリシリコン層3の第1部分3a’に代えたものと同様である。
次に、実施の形態3にかかる半導体装置の構造について説明する。図8は、実施の形態3にかかる半導体装置の一部を半導体基板のおもて面側から見たレイアウトを示す平面図である。図9は、実施の形態3にかかる半導体装置の一部を半導体基板のおもて面側から見たレイアウトの別の一例を示す平面図である。実施の形態3にかかる半導体装置60の全体を半導体基板10のおもて面側から見たレイアウトは、図1のゲートポリシリコン層3の第1部分3aを、図8,9のゲートポリシリコン層53,53’の第1部分53a,53a’に代えたものと同様である。
2 ゲートパッド
2a ゲートパッドの、ゲートパッド領域に配置された部分(第1部分)
2b ゲートパッドの、ゲート抵抗領域に配置された部分(第2部分)
3,53,53' ゲートポリシリコン層
3a,3a',53a,53a' ゲートポリシリコン層の、ゲートパッド領域に配置された部分(第1部分)
3b ゲートポリシリコン層の、ゲート抵抗領域に配置された部分(第2部分)
4 ゲートランナー
5 コンタクト電極
10 半導体基板
11 層間絶縁膜
11a〜11d コンタクトホール
12 パッシベーション膜
21 活性領域
22 エッジ終端領域
23 ゲートパッド領域
24 ゲート抵抗領域
31 n+型出発基板
32 n-型ドリフト領域
32' n-型領域
33 p型ベース領域
33' p型領域
34 n+型ソース領域
35 p+型コンタクト領域
36,36a〜36c トレンチ
37 ゲート絶縁膜
38 ゲート電極
40 n型電流拡散領域
41,42 p+型領域
43 ドレイン電極
51 n+型炭化珪素層
52 p型炭化珪素層
53c,53c' ゲートポリシリコン層の第1部分から突出する部分(第3部分)
60 半導体装置
L1 ゲートポリシリコン層の第2部分の長さ
L2 ゲートポリシリコン層の第2部分によるゲート抵抗の抵抗値を決めるコンタクトホール間の距離
L11 ソースパッドとゲートパッドとの間の距離
L12 ゲートポリシリコン層の外周端からゲートパッドの外周端までの距離
L13 ゲートランナーとゲートポリシリコン層との間の距離
L14 ゲートランナーの外周端からソースパッドの外周端までの距離
L15 ゲートポリシリコン層の第1部分の内周端からゲートパッドの外周端までの距離
W1 ゲートポリシリコン層の第2部分の幅
X 半導体基板のおもて面に平行な方向(第1方向)
Y 半導体基板のおもて面に平行でかつ第1方向と直交する方向(第2方向)
Z 深さ方向
Claims (12)
- オン状態のときに電流が流れ、MOS構造が構成された活性領域に、
半導体基板にゲート絶縁膜を介して設けられたゲート電極と、
前記半導体基板の第1主面に層間絶縁膜を介して設けられたゲートパッドと、
前記ゲートパッドと前記ゲート電極との間に直列に接続されたゲート抵抗と、
前記半導体基板の第1主面と前記層間絶縁膜との間に設けられて、前記層間絶縁膜を挟んで深さ方向に前記ゲートパッドの全面に対向し、かつ酸化膜によって前記半導体基板と電気的に絶縁されたゲートポリシリコン層と、
を備え、
前記ゲートパッドは、
配線が接合される第1部分と、
前記ゲート抵抗に接続された第2部分と、を連結してなり、
前記ゲートポリシリコン層は、
前記層間絶縁膜を挟んで深さ方向に前記ゲートパッドの第1部分の全面に対向する第1部分と、
前記層間絶縁膜を挟んで深さ方向に前記ゲートパッドの第2部分の全面に対向し、前記ゲートパッドの第2部分と前記ゲート電極との間に電気的に接続されて前記ゲート抵抗を構成する第2部分と、を連結してなり、
前記ゲートパッドが設けられた領域のESD耐量は、前記ゲート抵抗が設けられた領域のESD耐量よりも大きく、
前記ゲートパッドが設けられた領域のESD耐量は、前記活性領域のMOS構造が設けられた領域のESD耐量よりも大きいことを特徴とする半導体装置。 - 前記活性領域のMOS構造が設けられた領域のESD耐量は、前記ゲート抵抗が設けられた領域のESD耐量よりも大きいことを特徴とする請求項1に記載の半導体装置。
- 前記ゲートパッドが設けられた領域の静電容量は、前記ゲート抵抗が設けられた領域の静電容量よりも大きく、
前記ゲートパッドが設けられた領域の静電容量は、前記活性領域のMOS構造が設けられた領域の静電容量よりも大きいことを特徴とする請求項1または2に記載の半導体装置。 - 前記活性領域のMOS構造が設けられた領域の静電容量は、前記ゲート抵抗が設けられた領域の静電容量よりも大きいことを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記ゲートパッドと前記ゲートポリシリコン層とに挟まれた前記層間絶縁膜、または、前記ゲートポリシリコン層と前記半導体基板とに挟まれた前記酸化膜は、前記活性領域のMOS構造が設けられた領域の前記ゲート絶縁膜より厚いことを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- 前記ゲート抵抗が設けられた領域の前記酸化膜は、前記活性領域のMOS構造が設けられた領域の前記ゲート絶縁膜より厚いことを特徴とする請求項1〜5のいずれか一つに記載の半導体装置。
- 前記ゲートパッドと前記ゲートポリシリコン層とに挟まれた前記層間絶縁膜、または、前記ゲートポリシリコン層と前記半導体基板とに挟まれた前記酸化膜は、前記活性領域のMOS構造が設けられた領域の前記ゲート絶縁膜より誘電率が低いことを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
- 前記ゲート抵抗が設けられた領域の前記酸化膜は、前記活性領域のMOS構造が設けられた領域の前記ゲート絶縁膜より誘電率が低いことを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。
- 前記ゲートパッドが設けられた領域の前記酸化膜は、前記活性領域のMOS構造が設けられた領域の前記ゲート絶縁膜と共用され、
前記酸化膜と前記半導体基板との間に、薄膜が堆積された酸化膜が設けられていることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。 - 前記ゲートパッドと前記ゲートポリシリコン層とに挟まれた前記層間絶縁膜は、リンを含む酸化膜であり、
前記ゲート絶縁膜は、窒素を含む酸化膜であることを特徴とする請求項1〜9のいずれか一つに記載の半導体装置。 - 前記ゲート抵抗が設けられた領域の面積は、前記ゲートパッドが設けられた領域の面積より小さい、または、前記ゲート抵抗が設けられた領域の面積は、前記活性領域のMOS構造が設けられた領域の面積より小さいことを特徴とする請求項1〜10のいずれか一つに記載の半導体装置。
- 前記活性領域のMOS構造は、
第1導電型の前記半導体基板の第1主面の表面層に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられた第1導電型の第2半導体領域と、
前記半導体基板の、前記第1半導体領域を除く部分である第1導電型の第3半導体領域と、
前記第2半導体領域および前記第1半導体領域を貫通して前記第3半導体領域に達するトレンチと、
前記トレンチの内部に前記ゲート絶縁膜を介して設けられた前記ゲート電極と、からなるトレンチゲート構造を備え、
前記第1半導体領域および前記第2半導体領域に電気的に接続された第1電極と、
前記半導体基板の第2主面に電気的に接続された第2電極と、
を有し、
前記ゲートポリシリコン層は、前記ゲート電極または前記第1電極のいずれかに電気的に接続されていることを特徴とする請求項1〜11のいずれか一つに記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019047712A JP7234713B2 (ja) | 2019-03-14 | 2019-03-14 | 半導体装置 |
DE102020200862.0A DE102020200862A1 (de) | 2019-03-14 | 2020-01-24 | Halbleitervorrichtung |
US16/773,190 US11164859B2 (en) | 2019-03-14 | 2020-01-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019047712A JP7234713B2 (ja) | 2019-03-14 | 2019-03-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020150179A true JP2020150179A (ja) | 2020-09-17 |
JP7234713B2 JP7234713B2 (ja) | 2023-03-08 |
Family
ID=72241170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019047712A Active JP7234713B2 (ja) | 2019-03-14 | 2019-03-14 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11164859B2 (ja) |
JP (1) | JP7234713B2 (ja) |
DE (1) | DE102020200862A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112021004310T5 (de) | 2021-01-12 | 2023-05-25 | Rohm Co., Ltd. | Halbleiterbauteil |
WO2023189053A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
WO2023189054A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11362209B2 (en) * | 2019-04-16 | 2022-06-14 | Semiconductor Components Industries, Llc | Gate polysilicon feed structures for trench devices |
CN116646394A (zh) * | 2023-07-27 | 2023-08-25 | 深圳芯能半导体技术有限公司 | 一种具栅极电阻的igbt芯片及其制作方法 |
CN116779663A (zh) * | 2023-08-22 | 2023-09-19 | 合肥阿基米德电子科技有限公司 | 一种新型集成栅极电阻的igbt结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6020548A (ja) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | 集積回路における入力保護装置 |
JP2014216352A (ja) * | 2013-04-22 | 2014-11-17 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2015080162A1 (ja) * | 2013-11-28 | 2015-06-04 | ローム株式会社 | 半導体装置 |
JP2018078283A (ja) * | 2014-12-22 | 2018-05-17 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | ストライプ状トレンチゲート構造とゲートコネクタ構造とを有する半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197914A (ja) | 2001-12-28 | 2003-07-11 | Fuji Electric Co Ltd | 半導体装置 |
JP6274968B2 (ja) * | 2014-05-16 | 2018-02-07 | ローム株式会社 | 半導体装置 |
JP6020548B2 (ja) | 2014-12-26 | 2016-11-02 | ダイキン工業株式会社 | 蓄熱式空気調和機 |
KR102369553B1 (ko) * | 2015-12-31 | 2022-03-02 | 매그나칩 반도체 유한회사 | 저전압 트렌치 반도체 소자 |
US10522674B2 (en) | 2016-05-18 | 2019-12-31 | Rohm Co., Ltd. | Semiconductor with unified transistor structure and voltage regulator diode |
JP6942511B2 (ja) | 2016-05-18 | 2021-09-29 | ローム株式会社 | 半導体装置 |
EP3686929B1 (en) * | 2019-01-24 | 2023-09-20 | Infineon Technologies Dresden GmbH & Co . KG | Semiconductor die |
-
2019
- 2019-03-14 JP JP2019047712A patent/JP7234713B2/ja active Active
-
2020
- 2020-01-24 DE DE102020200862.0A patent/DE102020200862A1/de active Pending
- 2020-01-27 US US16/773,190 patent/US11164859B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6020548A (ja) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | 集積回路における入力保護装置 |
JP2014216352A (ja) * | 2013-04-22 | 2014-11-17 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2015080162A1 (ja) * | 2013-11-28 | 2015-06-04 | ローム株式会社 | 半導体装置 |
JP2018078283A (ja) * | 2014-12-22 | 2018-05-17 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | ストライプ状トレンチゲート構造とゲートコネクタ構造とを有する半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112021004310T5 (de) | 2021-01-12 | 2023-05-25 | Rohm Co., Ltd. | Halbleiterbauteil |
WO2023189053A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
WO2023189054A1 (ja) * | 2022-03-31 | 2023-10-05 | ローム株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP7234713B2 (ja) | 2023-03-08 |
US20200294989A1 (en) | 2020-09-17 |
US11164859B2 (en) | 2021-11-02 |
DE102020200862A1 (de) | 2020-09-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11107912B2 (en) | Trench gate semiconductor device with dummy gate electrode and manufacturing method of the same | |
JP2020150179A (ja) | 半導体装置 | |
JP6595915B2 (ja) | 半導体装置 | |
US8431998B2 (en) | Insulated gate semiconductor device | |
JP2007273931A (ja) | 電力用半導体素子、その製造方法及びその駆動方法 | |
JP7172317B2 (ja) | 半導体装置 | |
US6992340B2 (en) | Semiconductor device | |
EP3686929B1 (en) | Semiconductor die | |
JP6600017B2 (ja) | 半導体装置 | |
JP2003197914A (ja) | 半導体装置 | |
JP6956247B2 (ja) | 半導体装置 | |
JP2004014707A (ja) | 半導体装置 | |
CN114467181A (zh) | 半导体装置 | |
CN111834448A (zh) | 碳化硅半导体装置 | |
JP7139232B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP7139673B2 (ja) | 半導体装置 | |
JP7145817B2 (ja) | 半導体装置 | |
US20200395456A1 (en) | Semiconductor device | |
JP4103631B2 (ja) | 過電圧保護機能を有する半導体装置 | |
JP2024034977A (ja) | 半導体装置の製造方法 | |
JPH03138981A (ja) | 半導体素子 | |
JPH03231474A (ja) | 縦型電界効果トランジスタ | |
JPH0982723A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20220214 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230124 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20230119 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20230206 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7234713 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |