JP2020025070A5 - - Google Patents

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JP2020025070A5
JP2020025070A5 JP2019055846A JP2019055846A JP2020025070A5 JP 2020025070 A5 JP2020025070 A5 JP 2020025070A5 JP 2019055846 A JP2019055846 A JP 2019055846A JP 2019055846 A JP2019055846 A JP 2019055846A JP 2020025070 A5 JP2020025070 A5 JP 2020025070A5
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Japan
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module
transfer
process module
wafers
load lock
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JP2019055846A
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Japanese (ja)
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JP2020025070A (ja
JP7209567B2 (ja
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Priority to TW108126310A priority Critical patent/TWI850239B/zh
Priority to KR1020190090177A priority patent/KR102272823B1/ko
Priority to SG10201906930VA priority patent/SG10201906930VA/en
Priority to US16/523,541 priority patent/US11024514B2/en
Priority to CN201910694304.5A priority patent/CN110783188B/zh
Publication of JP2020025070A publication Critical patent/JP2020025070A/ja
Publication of JP2020025070A5 publication Critical patent/JP2020025070A5/ja
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JP2019055846A 2018-07-30 2019-03-25 エッチング方法およびエッチング装置 Active JP7209567B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW108126310A TWI850239B (zh) 2018-07-30 2019-07-25 蝕刻方法、及蝕刻裝置
KR1020190090177A KR102272823B1 (ko) 2018-07-30 2019-07-25 에칭 방법 및 에칭 장치
SG10201906930VA SG10201906930VA (en) 2018-07-30 2019-07-26 Etching method and etching apparatus
US16/523,541 US11024514B2 (en) 2018-07-30 2019-07-26 Etching method and etching apparatus
CN201910694304.5A CN110783188B (zh) 2018-07-30 2019-07-30 蚀刻方法和蚀刻装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018142005 2018-07-30
JP2018142005 2018-07-30

Publications (3)

Publication Number Publication Date
JP2020025070A JP2020025070A (ja) 2020-02-13
JP2020025070A5 true JP2020025070A5 (enExample) 2021-12-23
JP7209567B2 JP7209567B2 (ja) 2023-01-20

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JP2019055846A Active JP7209567B2 (ja) 2018-07-30 2019-03-25 エッチング方法およびエッチング装置

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JP (1) JP7209567B2 (enExample)
SG (1) SG10201906930VA (enExample)
TW (1) TWI850239B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7738439B2 (ja) * 2020-12-15 2025-09-12 東京エレクトロン株式会社 エッチング方法およびエッチング装置
US20220293430A1 (en) * 2021-03-12 2022-09-15 Applied Materials, Inc. Isotropic silicon nitride removal
KR102779338B1 (ko) * 2021-10-06 2025-03-12 주식회사 테스 기판 처리 방법
TWI836713B (zh) 2021-11-12 2024-03-21 南韓商Ｔｅｓ股份有限公司 基板處理方法
WO2024194953A1 (ja) * 2023-03-17 2024-09-26 株式会社Kokusai Electric エッチング方法、半導体装置の製造方法、処理装置、およびプログラム

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19706682C2 (de) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium
JP4221859B2 (ja) * 1999-02-12 2009-02-12 株式会社デンソー 半導体装置の製造方法
JP5206311B2 (ja) * 2008-10-24 2013-06-12 株式会社デンソー 半導体装置の製造方法
US8501630B2 (en) * 2010-09-28 2013-08-06 Tokyo Electron Limited Selective etch process for silicon nitride
US8999856B2 (en) * 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
KR20140022917A (ko) * 2011-08-25 2014-02-25 다이니폰 스크린 세이조우 가부시키가이샤 패턴 형성 방법
TWI476832B (zh) * 2011-09-28 2015-03-11 Tokyo Electron Ltd 蝕刻方法及裝置
US9093389B2 (en) * 2013-01-16 2015-07-28 Applied Materials, Inc. Method of patterning a silicon nitride dielectric film
JP6456131B2 (ja) * 2014-12-18 2019-01-23 キヤノン株式会社 基板の加工方法及び液体吐出ヘッドの製造方法
JP2018022830A (ja) * 2016-08-05 2018-02-08 東京エレクトロン株式会社 被処理体を処理する方法
US10062579B2 (en) * 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10692880B2 (en) * 2016-12-27 2020-06-23 Applied Materials, Inc. 3D NAND high aspect ratio structure etch
US10607850B2 (en) * 2016-12-30 2020-03-31 American Air Liquide, Inc. Iodine-containing compounds for etching semiconductor structures

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