JP2019520660A5 - - Google Patents

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Publication number
JP2019520660A5
JP2019520660A5 JP2019500870A JP2019500870A JP2019520660A5 JP 2019520660 A5 JP2019520660 A5 JP 2019520660A5 JP 2019500870 A JP2019500870 A JP 2019500870A JP 2019500870 A JP2019500870 A JP 2019500870A JP 2019520660 A5 JP2019520660 A5 JP 2019520660A5
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Japan
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address
decoder
access
region
memory
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JP2019500870A
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Japanese (ja)
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JP6761891B2 (ja
JP2019520660A (ja
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Priority claimed from US15/211,887 external-priority patent/US10403333B2/en
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JP2019500870A 2016-07-15 2016-09-23 柔軟なアドレスデコード機能を備えるメモリコントローラ Active JP6761891B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/211,887 US10403333B2 (en) 2016-07-15 2016-07-15 Memory controller with flexible address decoding
US15/211,887 2016-07-15
PCT/US2016/053358 WO2018013158A1 (en) 2016-07-15 2016-09-23 Memory controller with flexible address decoding

Publications (3)

Publication Number Publication Date
JP2019520660A JP2019520660A (ja) 2019-07-18
JP2019520660A5 true JP2019520660A5 (enExample) 2019-10-24
JP6761891B2 JP6761891B2 (ja) 2020-09-30

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JP2019500870A Active JP6761891B2 (ja) 2016-07-15 2016-09-23 柔軟なアドレスデコード機能を備えるメモリコントローラ

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US (1) US10403333B2 (enExample)
EP (1) EP3485383B1 (enExample)
JP (1) JP6761891B2 (enExample)
KR (1) KR102719994B1 (enExample)
CN (1) CN109478169B (enExample)
WO (1) WO2018013158A1 (enExample)

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