KR102719994B1 - 융통성 있는 어드레스 디코딩을 이용하는 메모리 제어기 - Google Patents

융통성 있는 어드레스 디코딩을 이용하는 메모리 제어기 Download PDF

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Publication number
KR102719994B1
KR102719994B1 KR1020197002561A KR20197002561A KR102719994B1 KR 102719994 B1 KR102719994 B1 KR 102719994B1 KR 1020197002561 A KR1020197002561 A KR 1020197002561A KR 20197002561 A KR20197002561 A KR 20197002561A KR 102719994 B1 KR102719994 B1 KR 102719994B1
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South Korea
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address
memory
decoder
zone
access
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KR20190019200A (ko
Inventor
케빈 엠. 브랜들
토마스 해밀턴
히데키 가나야마
케다르나스 바라크리시난
제임스 알. 마그로
구안하오 쉔
마크 파울러
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
  • Bus Control (AREA)
KR1020197002561A 2016-07-15 2016-09-23 융통성 있는 어드레스 디코딩을 이용하는 메모리 제어기 Active KR102719994B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/211,887 US10403333B2 (en) 2016-07-15 2016-07-15 Memory controller with flexible address decoding
US15/211,887 2016-07-15
PCT/US2016/053358 WO2018013158A1 (en) 2016-07-15 2016-09-23 Memory controller with flexible address decoding

Publications (2)

Publication Number Publication Date
KR20190019200A KR20190019200A (ko) 2019-02-26
KR102719994B1 true KR102719994B1 (ko) 2024-10-22

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KR1020197002561A Active KR102719994B1 (ko) 2016-07-15 2016-09-23 융통성 있는 어드레스 디코딩을 이용하는 메모리 제어기

Country Status (6)

Country Link
US (1) US10403333B2 (enExample)
EP (1) EP3485383B1 (enExample)
JP (1) JP6761891B2 (enExample)
KR (1) KR102719994B1 (enExample)
CN (1) CN109478169B (enExample)
WO (1) WO2018013158A1 (enExample)

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JP7168731B1 (ja) 2021-07-19 2022-11-09 Ｎｅｃプラットフォームズ株式会社 メモリアクセス制御装置、メモリアクセス制御方法、及び、メモリアクセス制御プログラム
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US12386735B2 (en) * 2021-09-22 2025-08-12 Intel Corporation Software driven dynamic memory allocation and address mapping for disaggregated memory pool
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Also Published As

Publication number Publication date
EP3485383A1 (en) 2019-05-22
WO2018013158A1 (en) 2018-01-18
US10403333B2 (en) 2019-09-03
EP3485383B1 (en) 2025-04-02
CN109478169B (zh) 2023-07-28
JP6761891B2 (ja) 2020-09-30
EP3485383A4 (en) 2020-04-22
CN109478169A (zh) 2019-03-15
US20180019006A1 (en) 2018-01-18
JP2019520660A (ja) 2019-07-18
KR20190019200A (ko) 2019-02-26

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