JP2019519917A - ファウンドリに依存しないウェファ後処理方法 - Google Patents
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- 238000012805 post-processing Methods 0.000 title claims abstract description 39
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 46
- 229910052710 silicon Inorganic materials 0.000 claims description 46
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000005350 fused silica glass Substances 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 8
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
Abstract
Description
Claims (20)
- アクティブ・サーフェスと、基板と、前記アクティブ・サーフェス及び前記基板の間に介在する中間層とを有するウェファに対する、ファウンドリに依存しない後処理方法であって:
ウェファ処理ファウンドリの出力イールドから前記ウェファを除去するステップ;
新たなサーフェスを露出させるために、前記基板を、前記中間層まで又は前記中間層の内側何ミクロンかまで薄化するステップ;及び
前記基板と比較して改善されたデバイス・パフォーマンスをもたらす別の材料基板に、前記新たなサーフェスを結合するステップ;
を有する後処理方法。 - 前記アクティブ・サーフェス及び前記基板のうち少なくとも何れかが、シリコン(Si)及びシリコン・ゲルマニウム(SiGe)のうち少なくとも何れかを含み、前記別の材料基板は高抵抗率材料を含む、請求項1に記載の後処理方法。
- 前記別の材料基板は、ガラス及び溶融シリカのうち少なくとも何れかを含む、請求項1に記載の後処理方法。
- 前記結合は酸化物ボンディングを含む、請求項1に記載の後処理方法。
- 前記薄化するステップは:
前記基板の外側の層を研磨するステップ;及び
前記基板の内側の層を化学機械研磨するステップ;
を含む、請求項1に記載の後処理方法。 - 前記薄化するステップは:
前記ウェファの中でビアの存在を認識するステップ;及び
前記ビアの位置では前記薄化の実行を回避するステップ;
を含む、請求項1に記載の後処理方法。 - 複数のファウンドリの中から類似するウェファを取得するステップ;
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上を実行するステップ;及び
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上の実行を最適化するステップ;
を更に有する請求項1に記載の後処理方法。 - アクティブ・サーフェスと、シリコン・ハンドルと、前記アクティブ・サーフェス及び前記シリコン・ハンドルの間に介在する埋め込み酸化物(BOX)層とを有するウェファに対する、ファウンドリに依存しない後処理方法であって:
ウェファ処理ファウンドリの出力イールドから前記ウェファを除去するステップ;
新たなサーフェスを露出させるために、前記シリコン・ハンドルを、前記BOX層まで又は前記BOX層の内側何ミクロンかまで薄化するステップ;及び
前記シリコン・ハンドルと比較して改善されたデバイス・パフォーマンスをもたらす別の材料基板に、前記新たなサーフェスを結合するステップ;
を有する後処理方法。 - 前記アクティブ・サーフェス及び前記シリコン・ハンドルのうち少なくとも何れかが、シリコン(Si)及びシリコン・ゲルマニウム(SiGe)のうち少なくとも何れかを含み、前記別の材料基板は高抵抗率材料を含む、請求項8に記載の後処理方法。
- 前記別の材料基板は、ガラス及び溶融シリカのうち少なくとも何れかを含む、請求項8に記載の後処理方法。
- 前記結合は酸化物ボンディングを含む、請求項8に記載の後処理方法。
- 前記薄化するステップは:
前記シリコン・ハンドルの外側の層を研磨するステップ;及び
前記シリコン・ハンドルの内側の層を化学機械研磨するステップ;
を含む、請求項8に記載の後処理方法。 - 前記薄化するステップは:
前記ウェファの中でビアの存在を認識するステップ;及び
前記ビアの位置では前記薄化の実行を回避するステップ;
を含む、請求項8に記載の後処理方法。 - 複数のファウンドリの中から類似するウェファを取得するステップ;
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上を実行するステップ;及び
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上の実行を最適化するステップ;
を更に有する請求項8に記載の後処理方法。 - アクティブ・サーフェスと、高抵抗率基板(HRES-SX)と、前記アクティブ・サーフェス及び前記HRES-SXの間に介在するニア・サブ・コレクタ(NS)とを有するウェファに対する、ファウンドリに依存しない後処理方法であって:
ウェファ処理ファウンドリの出力イールドから前記ウェファを除去するステップ;
新たなサーフェスを露出させるために、前記HRES-SXを、前記NSまで又は前記NSの内側何ミクロンかまで薄化するステップ;及び
前記HRES-SXと比較して改善されたデバイス・パフォーマンスをもたらす別の材料基板に、前記新たなサーフェスを結合するステップ;
を有する後処理方法。 - 前記アクティブ・サーフェス及び前記HRES-SXのうち少なくとも何れかが、シリコン(Si)及びシリコン・ゲルマニウム(SiGe)のうち少なくとも何れかを含み、前記別の材料基板は高抵抗率材料を含む、請求項15に記載の後処理方法。
- 前記別の材料基板は、ガラス及び溶融シリカのうち少なくとも何れかを含む、請求項15に記載の後処理方法。
- 前記結合は酸化物ボンディングを含む、請求項15に記載の後処理方法。
- 前記薄化するステップは:
前記HRES-SXの外側の層を研磨するステップ;及び
前記HRES-SXの内側の層を化学機械研磨するステップ;
を含む、請求項15に記載の後処理方法。 - 複数のファウンドリの中から類似するウェファを取得するステップ;
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上を実行するステップ;及び
前記類似するウェファの各々に対して、前記除去するステップ、薄化するステップ、及び結合するステップのうちの1つ以上の実行を最適化するステップ;
を更に有する請求項15に記載の後処理方法。
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Application Number | Priority Date | Filing Date | Title |
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US15/166,821 US10354910B2 (en) | 2016-05-27 | 2016-05-27 | Foundry-agnostic post-processing method for a wafer |
US15/166,821 | 2016-05-27 | ||
PCT/US2017/033330 WO2017205181A1 (en) | 2016-05-27 | 2017-05-18 | Foundry-agnostic post-processing method for a wafer |
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JP2019519917A true JP2019519917A (ja) | 2019-07-11 |
JP6707669B2 JP6707669B2 (ja) | 2020-06-10 |
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US (2) | US10354910B2 (ja) |
EP (1) | EP3465742B1 (ja) |
JP (1) | JP6707669B2 (ja) |
KR (1) | KR102274804B1 (ja) |
CN (1) | CN109314047A (ja) |
CA (1) | CA3024327A1 (ja) |
IL (1) | IL261798B (ja) |
SG (1) | SG11201808594XA (ja) |
TW (1) | TWI722191B (ja) |
WO (1) | WO2017205181A1 (ja) |
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2016
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JPH1126733A (ja) * | 1997-07-03 | 1999-01-29 | Seiko Epson Corp | 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置,アクティブマトリクス基板、液晶表示装置および電子機器 |
JP2004282063A (ja) * | 2003-02-28 | 2004-10-07 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
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JP2011049384A (ja) * | 2009-08-27 | 2011-03-10 | Fuji Electric Systems Co Ltd | 半導体装置の製造方法 |
JP2013543276A (ja) * | 2010-11-19 | 2013-11-28 | ソイテック | 無線周波数用途又は電力用途のための電子装置及びそのような装置を製造するためのプロセス |
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IL261798B (en) | 2021-10-31 |
US10354910B2 (en) | 2019-07-16 |
TWI722191B (zh) | 2021-03-21 |
JP6707669B2 (ja) | 2020-06-10 |
CA3024327A1 (en) | 2017-11-30 |
US20170345707A1 (en) | 2017-11-30 |
SG11201808594XA (en) | 2018-10-30 |
CN109314047A (zh) | 2019-02-05 |
US20190259653A1 (en) | 2019-08-22 |
TW201806004A (zh) | 2018-02-16 |
EP3465742A1 (en) | 2019-04-10 |
KR20190011277A (ko) | 2019-02-01 |
WO2017205181A1 (en) | 2017-11-30 |
EP3465742B1 (en) | 2024-04-03 |
IL261798A (en) | 2018-10-31 |
KR102274804B1 (ko) | 2021-07-07 |
US10679888B2 (en) | 2020-06-09 |
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