CN106601753B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN106601753B
CN106601753B CN201610786074.1A CN201610786074A CN106601753B CN 106601753 B CN106601753 B CN 106601753B CN 201610786074 A CN201610786074 A CN 201610786074A CN 106601753 B CN106601753 B CN 106601753B
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substrate
layer
handle substrate
interconnect structure
insulating layer
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CN106601753A (zh
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郑国裕
赵治平
蔡冠智
陈世雄
蔡维恭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的一些实施例涉及一种半导体器件。半导体器件包括衬底，衬底包括设置在绝缘层上方的硅层。衬底包括晶体管器件区域和射频(RF)区域。互连结构设置在衬底上方并且包括设置在介电结构内的多个金属层。处理衬底设置在互连结构的上表面上方。捕获层使互连结构与处理衬底分离。本发明的实施例还涉及形成半导体器件的方法。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体领域，更具体地涉及半导体器件及其形成方法。
背景技术
集成电路形成在半导体衬底上并且封装集成电路以形成所谓的芯片或微芯片。通常，集成电路形成在包括诸如硅的半导体材料的块状半导体衬底上。在最近几年里，出现了作为候选者的绝缘体上半导体(SOI)衬底。SOI衬底具有通过绝缘材料层与下面的处理衬底分离的有源半导体(如，硅)的薄层。绝缘材料层使有源半导体的薄层与处理衬底电隔离，从而减少形成在有源半导体的薄层内的器件的电流泄漏。有源半导体的薄层还提供了气体优势，诸如更快的开关时间和更低的操作电压，这使得SOI衬底广泛用于射频(RF)系统的高容量制造，诸如RF开关。
发明内容
本发明的实施例提供了一种半导体器件，包括：衬底，包括设置在绝缘层上方的半导体层，其中，所述衬底包括晶体管器件区域和射频(RF)区域；互连结构，设置在所述衬底上方并且包括设置在介电结构内的多个金属层；处理衬底，设置在所述互连结构的上表面上方；以及捕获层，使所述互连结构与所述处理衬底分离。
本发明的实施例还提供了一种形成半导体器件的方法，包括：提供第一衬底，所述第一衬底包括第一处理衬底、设置在所述第一处理衬底上方的绝缘层以及设置在所述绝缘层上方的半导体层；在所述第一衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；将包括第二处理衬底和捕获层的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层设置在所述第二处理衬底与所述互连结构的上表面之间；以及在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面。
本发明的实施例还提供了一种形成半导体器件的方法，包括：提供绝缘体上半导体(SOI)衬底，所述绝缘体上半导体衬底包括具有硅的第一处理衬底、设置在所述第一处理衬底上方的绝缘层、以及设置在所述绝缘层上方的硅层，其中，所述绝缘体上半导体衬底包括彼此横向分隔开的晶体管器件区域和射频(RF)区域；在所述绝缘体上半导体衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；将包括捕获层和由硅制成的第二处理衬底的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层使所述第二处理衬底与所述互连结构的上表面分离；在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面；以及形成接触焊盘以与所述绝缘层的下表面直接接触，其中，衬底贯通孔(TSV)垂直延伸穿过所述硅层并且穿过所述绝缘层以接触所述接触焊盘。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A示出了根据本发明的一些实施例的器件的一些实施例的截面图。
图1B示出了根据一些实施例的图1A的一部分的放大的截面图。
图2至图13出了截面图的一些实施例，这些截面图示出了制造的各个阶段中的形成IC的方法。
图14示出了根据一些实施例的形成器件的方法的一些实施例的流程图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
RF半导体器件通常制造在绝缘体上半导体(SOI)衬底上，并且RF半导体器件在高频下操作并且生成RF信号。对于这些RF器件，SOI衬底通常包括高电阻处理(handle)衬底、处理衬底上方的绝缘层以及绝缘层上方设置的半导体层。高电阻处理衬底具有低掺杂浓度，并且例如，可以表现出在从2千欧-厘米(kΩ-cm)至8kΩ-cm的范围内的电阻。在一些情况下，处理衬底的高电阻可以提高RF器件的射频(RF)性能，但是本发明中的构思在于以下事实，当载荷由于RF信号而脱离高电阻处理衬底的晶格时，高电阻处理衬底仍可以是涡电流的来源。可以表现出高频的这些涡电流是最终芯片中的噪声源。具体地，这些涡电流可以导致器件串扰和/或非线性信号失真。
为了防止这种串扰和非线性信号失真，本发明提出在SOI衬底上制造RF器件，该衬底包括处理衬底、绝缘材料层和有源半导体层。然而，不是将处理衬底留在最终器件中，在器件的最终封装之前，制造工艺从绝缘层的下侧去除处理衬底，从而使得处理衬底不再存在以用作涡电流的来源。
参考图1A，提供了根据本发明的器件100的一些实施例的截面图。器件100包括第一衬底106、设置在第一衬底106上方的互连结构112以及设置在互联结构112上方的第二衬底122。第一衬底106包括绝缘层110和有源半导体层108；互连结构112包括设置在介电结构116内的多个金属层(如，114a至114e)。诸如金属氧化物半导体场效应晶体管(MOSFET)111的一个或多个有源组件设置在第一衬底106的晶体管区域102中或上方，并且诸如电感器128、电容器130和/或电阻器131的一个或多个无源组件设置在第一衬底106的RF区域104上方。衬底贯通孔(TSV)118垂直延伸穿过半导体层108并且穿过绝缘层110。TSV 118将金属层(如，114a、114b、114c、...)电耦合至绝缘层110的下表面上的接触焊盘120。接触焊盘120的表面可以保持为通过封装或模制层121暴露，从而允许器件100通过焊料凸块、引线接合等安装至电路板或其他芯片，从而使得电路板或其他芯片可以电耦合至器件100上的有源和/或无源组件。
特别地，在一些实施例中，第一衬底106展示出不具有绝缘层110下面的处理衬底，并且因此，接触焊盘120直接接触绝缘层110的下表面。例如，参考图2至图13，下文将更加详细地介绍，通过工艺来制造器件100，在该工艺中，第一衬底106初始为SOI晶圆，该晶圆包括半导体层108、绝缘层110和绝缘层110下面的处理衬底。然而，在图1A中示出的最终器件中，去除了下面的处理衬底，以防止在器件操作期间下面的处理衬底用作涡电流源。因为绝缘层110是绝缘的(并且因此不易受涡电流影响)，所以下面的处理衬底的去除使得从第一衬底106的底部去除有问题的涡电流的来源。因此，与传统器件相比，器件100可以表现出更少的串扰和更少的失真。
为了补偿由于下面的处理衬底的去除而导致的第一衬底106的减少的厚度和结构硬度，并且为了提供足够的厚度以足以填充封装件以及为了在制造期间提供结构支撑，在互连结构112的上表面112u上方设置处理衬底124。可选但有利的捕获层126可以使互连结构112与处理衬底124分离。捕获层126配置为捕获由RF组件(如，电感器128和/或电容器130)激发的载荷以限制处理衬底124中的涡电流。例如，考虑以下情况，当施加合适的偏压时，电感器128和/或电容器130单独地或共同地生成RF信号，这可以在某种程度上在处理衬底124中激发载荷。捕获层126配置为捕获这些载荷以限制对应的涡电流。在一些实施例中，捕获层126可以示出为掺杂或未掺杂的多晶硅，或可以示出为无定型硅层。捕获层126可以在界面表面处与处理衬底124相遇(meet)，在一些情况下，界面表面表现出峰和谷，在其他情况下，界面表面基本平坦，或在其他情况下，界面表面通常是粗糙的。
图1B示出了一些实施例，其中，捕获层126由多晶硅制成并且具有多个晶粒边界(grain boundaries)132。晶粒边界132是位错或缺陷，其中捕获层126的原子在晶格内未处于适当的位置或未对准。晶粒边界132用作配置为捕获载荷(如，来自处理衬底124内的载荷)的复合中心(recombination center)。一旦在复合中心内被捕获，载荷的寿命就减少。因此，通过在捕获层126的晶粒边界132内捕获载荷，基本减少沿着处理衬底124的下表面的载荷的积聚，这缓解了器件100的操作期间的涡电流、串扰以及非线性失真。
在一些实施例中，介于处理衬底124与捕获层126之间的界面包括一系列峰134和谷136，这可以建立锯齿状轮廓。峰134和谷136有助于更小的晶粒尺寸，并且因此有助于处理衬底124的顶面附近的更多的晶粒边界。因此，在晶粒边界132处捕获大部分载荷，以缓解和/或防止涡电流。峰134和/或谷136可以为三角形形状、金字塔形状或圆锥形状等。在一些实施例中，峰134可以具有从相邻的谷(或更远的谷)的基底测量的在大约10nm至大约1um的范围内的高度h，并且在一些实施例中为大约0.5um。峰134还可以具有在从大约10nm至大约10um的范围内的宽度w，在一些实施例中为大约1um。在其他的实施例中，不是示出的平顶，峰134可以变尖和/或可以为圆形。类似地，在其他的实施例中，不是示出的变尖，谷136可以为平坦的底部或圆形。在一些实施例中，相邻的峰可以具有彼此相同的高度和/或宽度(相邻的谷也可以具有彼此相同的深度和/或宽度)，但是在其他的实施例中，峰也可以具有彼此不同的高度和/或不同的宽度(并且谷可以具有不同的深度和/或宽度)。在一些情况下，峰和/或谷服从高度和/或宽度的随机分布、服从高度和/或宽度的高斯分布、或服从一些其他的分布。
有利地，包括互联结构112上方的处理衬底124提供了增强的结构硬度以补偿绝缘层110下面缺少的处理衬底。另外，捕获层126有利地减少了作为处理衬底124中的潜在噪声源的涡电流，并且虽然是可选的，但是对于许多应用都是有利的。
参考图2至图13，一系列截面图共同示出了根据一些实施例的制造器件的方法。
图2示出了提供SOI衬底106'的一些实施例的截面图。如图2所示，SOI衬底106'是绝缘体上半导体(SOI)衬底，包括处理衬底202、设置在处理衬底202上方的绝缘层110、以及设置在绝缘层110上方的半导体层108。在许多实例中，SOI衬底106'可以采用盘状晶圆的形式。例如，这种晶圆可以具有如下尺寸：1inch(25mm)；2inch(51mm)；3inch(76mm)；4inch(100mm)；5inch(130mm)或125mm(4.9inch)；150mm(5.9inch，通常称为“6inch”)；200mm(7.9inch通常称为“8inch”)；300mm(11.8inch，通常称为“12inch”)；或450mm(17.7inch，通常称为“18inch”)。
处理衬底202可以具有足以提供SOI衬底106'的足够的结构硬度的厚度，以承受半导体加工操作。例如，在一些实施例中，处理衬底202具有在从大约200um至大约1000um的范围内的厚度，在一些实施例中为大约700um。在示例性实施例中，处理衬底202可以为低电阻率硅处理衬底，具有在介于几欧姆-厘米和几十欧姆-厘米之间的范围内的电阻，并且在一些实施例中在介于8欧姆-厘米和12欧姆-厘米之间的范围内。在可选的实施例中，处理衬底202可以为高电阻硅处理衬底，具有在介于几百和几千欧姆-厘米之间的电阻，并且在一些实施例中在介于2kΩ-cm至8kΩ-cm的范围内虽然可以使用高电阻或低电阻硅衬底，但是因为低电阻硅衬底更廉价，所以有利地使用低电阻硅衬底，并且由于在该制造工艺中将去除处理衬底202，所以其更大的电阻率未提供显著的优势。也可以使用诸如蓝宝石衬底的其他处理衬底。
在一些实施例中，绝缘层110可以具有在从小于一微米至几微米的范围内的厚度，这足以在处理衬底202与半导体层108之间提供电隔离。在一些实施例中，绝缘层110可以为二氧化硅，其具有大约3.9的介电常数。在其他实施例中，绝缘层110可以为低k介电材料。低k介电材料的非限制性实例包括(但不限于)：掺杂氟的二氧化硅、掺杂碳的二氧化硅、多孔二氧化硅、多孔掺杂碳的二氧化硅、旋涂有机聚合物电介质、和/或旋涂硅基聚合物电介质。
在一些实施例中，半导体层108为纯硅层，其可以表现出单晶体晶格并且可以为本征的(如，未掺杂的)或p型或n型掺杂的。在一些实施例中，半导体层108可以具有在从几微米向下至大约一纳米的范围内的厚度。半导体层108还可以是由来自周期表的两个货更多不同族的元素制成的半导体化合物。元素可以形成二元合金(两种元素，如GaAs)、三元合金(三种元素，如InGaAs或AlGaAs)、或四元合金(四种元素，如AlInGaP)。半导体层108可以包括掺杂区域、外延层、形成在半导体层中或上的绝缘层、形成在半导体层中或上的光刻胶层、和/或形成在半导体层中或上的导电层。
在图3中，诸如MOSFET 111和/或场效应晶体管(FET)的有源组件形成在半导体层108的晶体管区域102中或上方。形成浅沟槽隔离(STI)区域117，其中绝缘材料围绕半导体层108的材料的岛状物(island)。形成栅电极123，在栅电极123的相对侧壁上形成侧壁间隔件125，以及在侧壁间隔件125的相对侧部上形成源极/漏极区域119。栅极电介质127使栅电极123与半导体层中的分离源极/漏极区域119的沟道区域分离。在一些实施例中，栅电极123包括多晶硅或金属，侧壁间隔件125包括氮化硅，以及栅极电介质127包括二氧化硅或高k电介质。虽然未示出，但是晶体管111还可以采用其他形式，诸如finFET器件、双极结型晶体管、浮置栅极晶体管等。例如可以由多晶硅135制成并且可以通过栅极电介质和/或其他电介质129与半导体层108隔离的电阻器131可以形成在RF区域104中。介电层133在栅电极123和源极/漏极区域119的上表面上方延伸。介电层133可以包括低k介电材料或二氧化硅。
在图4中，形成源极/漏极接触件150以提供通过穿过介电层133至源极/漏极区域119的欧姆连接，并且形成栅极接触件152以提供至栅电极123的顶面的欧姆连接。在一些实施例中，例如，源极/漏极接触件150和/或栅极接触件152可以包括铜、钨、铝、金、钛或氮化钛。另外，形成衬底贯通孔(TSV)118。示出的TSV 118向下延伸穿过介电层133、穿过半导体层108、以及穿过绝缘层110。在其他的实施例中，TSV 118也可以向下部分地延伸穿过或完全延伸穿过处理衬底202。例如，TSV 118可以由铜、钨、铝、金、钛或氮化钛制成，并且可以由于源极/漏极接触件150和/或栅极接触件152相同或不同的材料制成。通常通过与源极/漏极接触件和/或栅极接触件分离的光掩模和/或蚀刻来形成TSV 118。
如图5所示，在SOI衬底106'上方形成互连结构112。通过如下方式来形成互连结构112：形成诸如低k介电材料、氮化物或二氧化硅介电层的第一介电层154，并且然后在第一介电层154上方形成一个或多个光刻胶掩模。利用适当位置中的光刻胶掩模，进行蚀刻以在第一介电层154中形成沟槽开口和/或通孔开口。然后，沉积金属以填充第一介电层154中的开口，从而形成与金属1层对应的通孔和/或金属线156。在一些实施例中，使用铜填充第一介电层154中的开口，从而通孔和金属1线由铜制成。在使用铜的实施例中，通过利用扩散阻挡层来对开口进行加衬，然后在扩散阻挡层上方形成铜晶种层，以及使用电镀工艺积聚铜以填充开口。扩散阻挡层通常具有高导电率，以维持良好的电接触，同时维持足够低的铜扩散率，以足以化学隔离这些痛导体膜与下面的结构。钴、钌、钽、氮化钽、氧化铟、氮化钨和氮化钛是可以用于扩散阻挡层的材料的非限制性实例。在生长金属以填充开口之后，进行化学机械平坦化(CMP)操作以在平面154a处平坦化第一金属层和第一电介质。然后形成第二介电层158，在第二介电层158中形成开口，以及沉积金属以形成通孔和金属2线160。以这种方式形成附加的介电层和金属层，直到形成互连结构112。如图5所示，互连结构112可以包括诸如电感器128和/或电容器130的RF组件，并且该组件形成在SOI衬底106'的RF区域104上方。
在图6中，提供诸如块状硅晶圆的第二处理衬底124'。第二处理衬底124'可以具有在介于300um和1000um之间的范围内的厚度，在一些实施例中为大约700um。在一些实施例中，第二处理衬底124'可以具有比处理衬底202的电阻率大的电阻率。例如，在一些实施例中，第二处理衬底124'可以具有介于几百和几千欧姆-厘米之间的范围内的电阻率，并且在一些实施例中在介于2kΩ-cm至8kΩ-cm的范围内，这可以帮助减少最终器件中的涡电流。在一些情况下，提供第二处理衬底124'以用于结构支撑，并且因此，在一些实施例中可以展示出缺少器件部件并且缺少互连部件。在许多实例中，第二处理衬底124'可以采用盘状晶圆的形式。例如，这种晶圆可以具有如下尺寸：1inch(25mm)；2inch(51mm)；3inch(76mm)；4inch(100mm)；5inch(130mm)或125mm(4.9inch)；150mm(5.9inch，通常称为“6inch”)；200mm(7.9inch通常称为“8inch”)；300mm(11.8inch，通常称为“12inch”)；或450mm(17.7inch，通常称为“18inch”)；并且通常具有与SOI衬底106'相同的直径。
在图7中，蚀刻第二处理衬底124'的顶面以形成峰134和谷136。通过如下方式来创建峰134和谷136：首先使用光掩模(未示出)来在顶面上限定图案，并且然后将顶面暴露于蚀刻剂702，以制造具有峰和谷的粗糙顶面。在其他的实施例中，可以通过机械损坏第二处理衬底124'的顶面(如，微擦伤、喷砂等)或通过执行溅射、沉积或自组装单层来损害第二处理衬底124'。在一些实施例中，峰和谷包括锯齿状形状的突起和对应的缺口，其中，单个“齿”的峰和谷以固定间隔或随机间隔分隔开。在其他的实施例中，峰和谷包括具有不同的晶格方向和几何体的随机形状的突起。在一些实施例中，蚀刻剂702可以包括干蚀刻剂(如，等离子体蚀刻剂、RIE蚀刻剂等)或湿蚀刻剂(如，氢氟酸)。
在图8中，捕获层126形成在峰134和谷136上方，从而在捕获层126与第二处理衬底124'之间建立界面。因此，提供第二衬底122。在一些实施例中，捕获层126可以为多晶硅层。在其他的实施例中，捕获层126可以包括具有掺杂物质的无定型硅。在各个实施例中，掺杂物质可以包括氩(Ar)、碳(C)和/或锗(Ge)。例如，在一些情况下，可以通过使用CMP来平坦化捕获层的最远离第二处理衬底124'的表面802，以使其更适合于接合。
在图9中，SOI衬底106'和互连结构112接合至第二衬底122。该接合可以采用诸如熔融结合或通过环氧树脂接合的多种形式中的一种。在一些实施例中，在接合之前，可以在捕获层126的下表面上方形成氧化物，并且然后，捕获层126的下表面上的氧化物可以通过退火工艺接合至互连结构112的上表面。
在图10中，去除处理衬底202。在一些实施例中，使用两阶段工艺来去除处理衬底202。在第一阶段期间，使用研磨工艺来减薄处理衬底，例如减少第一距离d1。研磨工艺可以使用相当粗糙的表面，并且因此相当快地向下研磨处理衬底202的距离d1。在完成研磨工艺之后，例如按照确定的预定时间或通过执行测量以指示已经去除了预定的距离d1；进行化学机械平坦化(CMP)操作以去除处理衬底202的第二、剩余的部分d2。CMP操作通常使用没有研磨那么粗糙的抛光垫，从而提供比研磨更加光滑、更加均匀的表面。例如，可以在预定的时间过去之后或当测量结果指示处理衬底202已经被完全去除，结束CMP操作。将理解，在一些实施例中，减薄的处理衬底202的一些部分可以留在绝缘层110的底面上。
图11示出了进行CMP之后的图10的结构。在图11的实例中，暴露TSV 118的下部。
在图12中，接触焊盘120形成为与TSV 118的下部直接接触。在一些实施例中，接触焊盘120与绝缘层110的下侧直接接触。例如，接触焊盘120可以由铜、钨、铝、金、钛或氮化钛制成。在一些实施例中，通过以下方式来制造接触焊盘120：在绝缘层110的底面上形成金属层，并且然后图案化金属层，例如使用光刻掩模并且利用适当位置中的光刻掩模来执行金属层的蚀刻。注意，图12示出了若干不同的TSV 118、118a、118b和分别对应的接触焊盘120、120a、120b，以突出一些实例。TSV 118在金属1层、介电层133、半导体层108、和绝缘层110之间延伸；而第二TSV 118a从电阻器131的下表面延伸穿过电介质129、半导体层108和绝缘层110。第三TSV 118b从金属2线延伸穿过第二介电层158、第一介电层154、介电层133、穿过半导体层108、以及穿过绝缘层110。
在形成接触焊盘120之后，通常仍为盘状晶圆形状的结构可以可选地接合至其他衬底以建立3D IC，并且可以切割或划割为单独的管芯或集成电路。然后，在图13中，形成封装层121以覆盖绝缘层110的下表面。封装层121可以沿着器件的侧壁延伸以覆盖第二处理衬底122的上表面。例如，封装层121可以由陶瓷或聚合物材料制成，并且可以保护器件免于极端环境、腐蚀作用、泥土、灰尘、水、蒸汽等。
图14示出了根据本发明的一些实施例的制造器件的方法1400的一些实施例的流程图。虽然本文将所公开的方法1400示出和描述为一系列的步骤或事件，但是应当理解，所示出的这些步骤或事件的顺序不应解释为限制意义。例如，一些步骤可以以不同顺序发生和/或与除了本文所示和/或所述步骤或事件之外的其他步骤或事件同时发生。另外，并不要求所有示出的步骤都用来实施本文所描述的一个或多个方面或实施例。此外，可在一个或多个分离的步骤和/或阶段中执行本文所述步骤的一个或多个。此外，虽然为了简洁，将图14描述为与图2至图13相关，但是应当理解，图2至图13中公开的结构不限制于该方法，相反，可以代表独立于该方法的结构。类似地，虽然结合图2至图13来描述图14的方法，但是应当理解，该方法不限制于在图2至图13所公开的结构，相反，可以代表独立于图2至图13中所公开的结构的方法。
在步骤1402中，提供SOI衬底。第一衬底包括第一处理衬底、设置在第一处理衬底上方的绝缘层以及设置在绝缘层上方的半导体层。因此，例如，步骤1402可以对应于图2。
在步骤1404中，在SOI衬底上方形成互连结构。互连结构包括设置在介电结构内的多个金属层。因此，例如，步骤1404可以对应于图5。
在步骤1406中，将第二衬底接合至互连结构的上表面。在一些实施例中，第二衬底包括第二处理衬底和捕获层。在一些这样的实施例中，在接合之后，捕获层设置在第二处理衬底与互连结构的上表面之间。因此，例如，步骤1406可以对应于图9。
在步骤1408中，在将第二衬底接合至互连结构的上表面之后，去除第一处理衬底以暴露绝缘层的下表面。因此，例如，步骤1408可以对应于图10。
在步骤1410中，在去除第一处理衬底之后，形成接触焊盘以与绝缘层的下表面直接接触。衬底贯通孔(TSV)垂直延伸穿过绝缘层和半导体层并且将接触焊盘电耦合至互连结构的金属层。因此，例如，步骤1410可以对应于图12。
因此，如可以从以上理解的，本发明的一些实施例涉及一种器件。器件包括衬底，衬底包括设置在绝缘层上方的硅层。衬底包括晶体管器件区域和射频(RF)区域。互连结构设置在衬底上方并且包括设置在介电结构内的多个金属层。处理衬底设置在互连结构的上表面上方。捕获层使互连结构与处理衬底分离。
其他实施例涉及一种方法。在该方法中，提供第一衬底。第一衬底包括第一处理衬底、设置在第一处理衬底上方的绝缘层以及设置在绝缘层上方的半导体层。在衬底上方形成互连结构。互连结构包括设置在介电结构内的多个金属层。将包括第二处理衬底和捕获层的第二衬底接合至互连结构的上表面。在接合之后，捕获层设置在第二处理衬底与互连结构的上表面之间。然后，去除第一处理衬底以暴露绝缘层的下表面。
又一其他的实施例涉及一种方法。在该方法中，提供SOI衬底。SOI衬底包括第一处理衬底、设置在第一处理衬底上方的绝缘层以及设置在绝缘层上方的硅层。SOI衬底包括彼此横向分离开的晶体管器件区域和射频(RF)区域。在SOI衬底上方形成互连结构。互连结构包括设置在介电结构内的多个金属层。将包括捕获层和由硅制成的第二处理衬底的第二衬底接合至互连结构的上表面。在接合之后，捕获层使第二处理衬底与互连结构的上表面分离。然后，去除第一处理衬底以暴露绝缘层的下表面；以及形成接触焊盘以与绝缘层的下表面直接接触。衬底贯通孔(TSV)垂直延伸穿过硅层并且穿过绝缘层。
本发明的实施例提供了一种半导体器件，包括：衬底，包括设置在绝缘层上方的半导体层，其中，所述衬底包括晶体管器件区域和射频(RF)区域；互连结构，设置在所述衬底上方并且包括设置在介电结构内的多个金属层；处理衬底，设置在所述互连结构的上表面上方；以及捕获层，使所述互连结构与所述处理衬底分离。
根据本发明的一个实施例，半导体器件还包括：接触焊盘，设置为与所述衬底的绝缘层的下表面直接物理接触；以及衬底贯通孔，垂直延伸穿过所述半导体层和所述绝缘层并且将所述接触焊盘电耦合至所述互连结构的金属层。
根据本发明的一个实施例，其中，所述处理衬底包括硅衬底，并且所述捕获层包括在非平面界面处与所述硅衬底相遇的多晶硅层。
根据本发明的一个实施例，其中，所述非平面界面包括从所述硅衬底向下延伸至所述捕获层中的一系列峰。
根据本发明的一个实施例，其中，所述射频区域包括射频器件，所述射频器件布置在所述互连结构中并且配置为发出射频信号，其中，所述捕获层配置为捕获由所述射频信号激发的载荷以限制所述处理衬底中的涡电流。
根据本发明的一个实施例，半导体器件还包括：封装层，覆盖所述绝缘层的下表面并且沿着所述器件的侧壁延伸以覆盖所述处理衬底的上表面。
本发明的实施例还提供了一种形成半导体器件的方法，包括：提供第一衬底，所述第一衬底包括第一处理衬底、设置在所述第一处理衬底上方的绝缘层以及设置在所述绝缘层上方的半导体层；在所述第一衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；将包括第二处理衬底和捕获层的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层设置在所述第二处理衬底与所述互连结构的上表面之间；以及在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面。
根据本发明的一个实施例，方法还包括：在去除所述第一处理衬底之后，形成接触焊盘以与所述第一衬底的绝缘层的下表面直接物理接触，其中，衬底贯通孔(TSV)垂直延伸穿过所述半导体层和所述绝缘层并且将所述接触焊盘电耦合至所述互连结构的金属层。
根据本发明的一个实施例，其中，所述第一处理衬底和所述第二处理衬底具有不同的欧姆电阻。
根据本发明的一个实施例，其中，所述第一处理衬底具有介于8欧姆-厘米和12欧姆-厘米之间的电阻。
根据本发明的一个实施例，其中，所述第一处理衬底具有第一欧姆电阻，并且所述第二处理衬底具有第二欧姆电阻，所述第二欧姆电阻比所述第一欧姆电阻大一个数量级或以上。
根据本发明的一个实施例，其中，所述第二处理衬底包括硅衬底，并且所述捕获层包括无定型硅层。
根据本发明的一个实施例，其中，所述第二处理衬底包括硅衬底，并且所述捕获层包括在非平面界面处与所述硅衬底相遇的多晶硅层。
根据本发明的一个实施例，其中，所述非平面界面包括从所述硅衬底向下延伸至所述捕获层中的一系列峰。
根据本发明的一个实施例，其中，通过在所述硅衬底的表面上方形成光掩模、并且蚀刻所述硅衬底的表面以形成一系列峰和谷来形成所述非平面界面，并且所述捕获层直接形成在所述一系列峰和谷上方。
根据本发明的一个实施例，其中，射频(RF)器件布置在所述互连结构中并且配置为发出射频信号，其中，所述捕获层配置为捕获由所述射频信号激发的载荷以限制所述第二处理衬底中的涡电流。
本发明的实施例还提供了一种形成半导体器件的方法，包括：提供绝缘体上半导体(SOI)衬底，所述绝缘体上半导体衬底包括具有硅的第一处理衬底、设置在所述第一处理衬底上方的绝缘层、以及设置在所述绝缘层上方的硅层，其中，所述绝缘体上半导体衬底包括彼此横向分隔开的晶体管器件区域和射频(RF)区域；在所述绝缘体上半导体衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；将包括捕获层和由硅制成的第二处理衬底的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层使所述第二处理衬底与所述互连结构的上表面分离；在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面；以及形成接触焊盘以与所述绝缘层的下表面直接接触，其中，衬底贯通孔(TSV)垂直延伸穿过所述硅层并且穿过所述绝缘层以接触所述接触焊盘。
根据本发明的一个实施例，其中，所述第一处理衬底具有比所述第二处理衬底小的欧姆电阻。
根据本发明的一个实施例，方法还包括：在所述硅层的晶体管器件区域的上表面上形成栅极电介质；在所述栅极电介质上方形成栅电极，其中，所述金属层中的至少一个耦合至所述栅电极。
根据本发明的一个实施例，其中，所述衬底贯通孔将所述接触焊盘电耦合至所述金属层中的所述至少一个。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (17)

1.一种半导体器件，包括：
衬底，包括设置在绝缘层上方的半导体层，其中，所述衬底包括晶体管器件区域和射频(RF)区域；
互连结构，设置在所述衬底上方并且包括设置在介电结构内的多个金属层；
处理衬底，设置在所述互连结构的上表面上方；以及
捕获层，使所述互连结构与所述处理衬底分离，
其中，所述处理衬底包括硅衬底，并且所述捕获层包括在具有锯齿状轮廓的非平面界面处与所述硅衬底相遇的多晶硅层，其中所述锯齿状轮廓的缺口朝向所述处理衬底，所述锯齿状轮廓的非平面界面包括一系列峰，所述一系列峰的间隔和深度与所述多晶硅层的晶粒边界的间隔和深度不同。
2.根据权利要求1所述的半导体器件，还包括：
接触焊盘，设置为与所述衬底的绝缘层的下表面直接物理接触；以及
衬底贯通孔，垂直延伸穿过所述半导体层和所述绝缘层并且将所述接触焊盘电耦合至所述互连结构的金属层。
3.根据权利要求1所述的半导体器件，其中，所述非平面界面包括从所述硅衬底向下延伸至所述捕获层中的所述一系列峰。
4.根据权利要求1所述的半导体器件，其中，所述射频区域包括射频器件，所述射频器件布置在所述互连结构中并且配置为发出射频信号，其中，所述捕获层配置为捕获由所述射频信号激发的载荷以限制所述处理衬底中的涡电流。
5.根据权利要求1所述的半导体器件，还包括：封装层，覆盖所述绝缘层的下表面并且沿着所述半导体器件的侧壁延伸以覆盖所述处理衬底的上表面。
6.一种形成半导体器件的方法，包括：
提供第一衬底，所述第一衬底包括第一处理衬底、设置在所述第一处理衬底上方的绝缘层以及设置在所述绝缘层上方的半导体层；
在所述第一衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；
将包括第二处理衬底和捕获层的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层设置在所述第二处理衬底与所述互连结构的上表面之间；以及
在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面；
其中，所述第二处理衬底包括硅衬底，并且所述捕获层包括在具有锯齿状轮廓的非平面界面处与所述硅衬底相遇的多晶硅层，并且通过在所述硅衬底的表面上方形成光掩模、并且蚀刻所述硅衬底的表面以形成一系列峰和谷来形成所述非平面界面，并且所述捕获层直接形成在所述一系列峰和谷上方。
7.根据权利要求6所述的方法，还包括：
在去除所述第一处理衬底之后，形成接触焊盘以与所述第一衬底的绝缘层的下表面直接物理接触，其中，衬底贯通孔(TSV)垂直延伸穿过所述半导体层和所述绝缘层并且将所述接触焊盘电耦合至所述互连结构的金属层。
8.根据权利要求6所述的方法，其中，所述第一处理衬底和所述第二处理衬底具有不同的欧姆电阻。
9.根据权利要求6所述的方法，其中，所述第一处理衬底具有介于8欧姆-厘米和12欧姆-厘米之间的电阻。
10.根据权利要求6所述的方法，其中，所述第一处理衬底具有第一欧姆电阻，并且所述第二处理衬底具有第二欧姆电阻，所述第二欧姆电阻比所述第一欧姆电阻大一个数量级或以上。
11.根据权利要求6所述的方法，其中，所述第二处理衬底包括硅衬底，并且所述捕获层包括无定型硅层。
12.根据权利要求6所述的方法，其中，所述非平面界面包括从所述硅衬底向下延伸至所述捕获层中的一系列峰。
13.根据权利要求6所述的方法，其中，射频(RF)器件布置在所述互连结构中并且配置为发出射频信号，其中，所述捕获层配置为捕获由所述射频信号激发的载荷以限制所述第二处理衬底中的涡电流。
14.一种形成半导体器件的方法，包括：
提供绝缘体上半导体(SOI)衬底，所述绝缘体上半导体衬底包括具有硅的第一处理衬底、设置在所述第一处理衬底上方的绝缘层、以及设置在所述绝缘层上方的硅层，其中，所述绝缘体上半导体衬底包括彼此横向分隔开的晶体管器件区域和射频(RF)区域；
在所述绝缘体上半导体衬底上方形成互连结构，其中，所述互连结构包括设置在介电结构内的多个金属层；
将包括捕获层和由硅制成的第二处理衬底的第二衬底接合至所述互连结构的上表面，其中，在接合之后，所述捕获层使所述第二处理衬底与所述互连结构的上表面分离；
在所述接合之后，去除所述第一处理衬底以暴露所述绝缘层的下表面；以及
形成接触焊盘以与所述绝缘层的下表面直接接触，其中，衬底贯通孔(TSV)垂直延伸穿过所述硅层并且穿过所述绝缘层以接触所述接触焊盘，
其中，所述捕获层在具有锯齿状轮廓的非平面界面处与所述第二处理衬底相遇，并且通过在所述第二处理衬底的表面上方形成光掩模、并且蚀刻所述第二处理衬底的表面以形成一系列峰和谷来形成所述非平面界面，并且所述捕获层直接形成在所述一系列峰和谷上方。
15.根据权利要求14所述的方法，其中，所述第一处理衬底具有比所述第二处理衬底小的欧姆电阻。
16.根据权利要求14所述的方法，还包括：
在所述硅层的晶体管器件区域的上表面上形成栅极电介质；
在所述栅极电介质上方形成栅电极，其中，所述金属层中的至少一个耦合至所述栅电极。
17.根据权利要求16所述的方法，其中，所述衬底贯通孔将所述接触焊盘电耦合至所述金属层中的所述至少一个。
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