JP2019509636A - オプトエレクトロニクス部品およびオプトエレクトロニクス部品を製造するための方法 - Google Patents
オプトエレクトロニクス部品およびオプトエレクトロニクス部品を製造するための方法 Download PDFInfo
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- JP2019509636A JP2019509636A JP2018544099A JP2018544099A JP2019509636A JP 2019509636 A JP2019509636 A JP 2019509636A JP 2018544099 A JP2018544099 A JP 2018544099A JP 2018544099 A JP2018544099 A JP 2018544099A JP 2019509636 A JP2019509636 A JP 2019509636A
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Abstract
Description
導体/絶縁体、
絶縁体/導体、
絶縁体/絶縁体、および/または、
導体/導体、
が存在し、第1の接続層の材料が斜線の左側に示され、第2の接続層の材料が斜線の右側に示される。
・ ハイブリッド層/ハイブリッド層
・ ハイブリッド層/均一層
・ 均一層/ハイブリッド層
・ 均一層/均一層
で形成され、第1の接続層のタイプが斜線の左側に示され、第2の接続層のタイプが斜線の右側に示される。
キャリアと、第1の接続層および第2の接続層を含む接続層ペアと、をさらに含み、
・ 半導体ボディは、キャリアに配置され、
・ 第1の接続層は、半導体ボディとキャリアとの間に配設されて半導体ボディに接続され、
・ 第2の接続層は、第1の接続層とキャリアとの間に配設され、
・ 第1の接続層および第2の接続層から選択された少なくとも1つの層は、放射透過性および導電性の酸化物を含有し、
・ 第1の接続層および第2の接続層は、少なくとも1つまたは複数の接続領域のうちの領域で互いに直接接続され、したがって、接続層ペアは、キャリアに対する半導体ボディの機械的接続部に包含される。
10a、10b、10c 半導体ボディ
12 活性領域
14 第1の半導体層
16 第2の半導体層
20 基板
30a、30b、30c 接続層ペア
32 第1の接続層
34 第2の接続層
321 第1の境界面
341 第2の境界面
40 複合体要素
50 オプトエレクトロニクスデバイス
60 キャリア
62、64、66、68 端子領域
72 第1のタイプの接続導体
74 第2のタイプの接続導体
76 絶縁材料
78a、78b、78c 接続導体
80、82 導電性サブ領域
92、94、96、98 電子要素
100 第1の複合体
200 第2の複合体
112、114、116、118 接触部
120 終端接触部
I 絶縁性サブ領域
C 導電性サブ領域
Claims (20)
- 光学的活性領域(12)を含む半導体ボディ(10a、10b、10c)と、キャリア(60)と、第1の接続層(32)および第2の接続層(34)を含む接続層ペア(30a、30b、30c)と、を備えるオプトエレクトロニクスデバイス(50)であって、
前記半導体ボディは、前記キャリアに配置されており、
前記第1の接続層は、前記半導体ボディと前記キャリアとの間に配設されて前記半導体ボディに接続されており、
前記第2の接続層は、前記第1の接続層と前記キャリアとの間に配設されており、
前記第1の接続層および前記第2の接続層から選択された少なくとも1つの層は、放射透過性および導電性の酸化物を含有しており、
前記第1の接続層および前記第2の接続層は、少なくとも1つまたは複数の接続領域のうちいずれかの領域で互いに直接接続されており、したがって、前記接続層ペアは、前記キャリアに対する前記半導体ボディの当該機械的接続部に包含されており、
前記第1の接続層(32)および/または前記第2の接続層(34)は、前記それぞれの層内で互いに電気的に絶縁されている複数の導電性サブ領域(80、82)を含み、それらのサブ領域のうちの少なくとも2つは、前記光学的活性領域(12)の異なる側で前記半導体ボディ(10a、10b、10c)に導電接続されている、
オプトエレクトロニクスデバイス(50)。 - 前記第1の接続層(32)および第2の接続層(34)、のすべては、放射透過性および導電性の酸化物を含有し、
前記第1の接続層(32)および第2の接続層(34)、のうちの少なくとも1つまたはすべては、電気的絶縁性の酸化物を含有する、
請求項1に記載のオプトエレクトロニクスデバイス。 - 前記導電性サブ領域(80、82)は、TCO材料を含有する、またはTCO材料からなる、
請求項1または2の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記デバイス(50)は、前記半導体ボディ(10a、10b、10c)の中に延びる接続導体(72、74、78)を含み、前記接続導体は、前記半導体ボディの中で前記活性領域から、また、前記活性領域の少なくとも1つの側で前記半導体ボディからも、電気的に絶縁される、
請求項1〜3の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記少なくとも2つの導電性サブ領域のうちの第1のサブ領域(80)は、前記接続層ペア(30a、30b、30c)に対向している前記活性領域の側で、前記半導体ボディ(10a、10b、10c)に導電接続されており、前記少なくとも2つのサブ領域のうちの第2のサブ領域(82)は、前記接続層ペアの反対側に対向している前記光学的活性領域(12)の側で、前記半導体ボディに前記接続導体(72、74、78)を介して導電接続されている、
請求項1〜4の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記接続導体(72、74)は、前記半導体ボディ(10a、10b、10c)に対向している前記接続層ペア(30a、30b、30c)の側で、前記第1の接続層の導電性サブ領域に導電接続されおり、前記導電性サブ領域と前記接続導体との間のコンタクト表面の面積は、前記半導体ボディに対向している前記導電性サブ領域の表面の面積よりも小さい、
請求項4または5の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記接続導体(78)は、前記接続層ペア(30a、30b、30c)を貫通し、前記接続層ペアから電気的に絶縁されている、
請求項4に記載のオプトエレクトロニクスデバイス。 - 前記接続導体(72、74、78)は、前記半導体ボディ(10a、10b、10c)全体を貫通している、
請求項4〜7の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記第1の接続層(32)および/または前記第2の接続層(34)は、構造化されて1つまたは複数のガス充填済み凹部を含み、当該凹部によりそれぞれの接続層の少なくとも2つの導電性サブ領域(80、82)が互いに電気的に絶縁されている、
請求項1〜8の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記第1の接続層(32)および/または前記第2の接続層(34)は、ハイブリッド層として形成されており、前記それぞれのハイブリッド層は、1つまたは複数の導電性サブ領域(C)、および、1つまたは複数の電気的絶縁性サブ領域(I)を含む、
請求項1〜9の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記第1の接続層(32)および/または前記第2の接続層(34)は、その延在部分にわたって材料組成が変わらない、
請求項1〜8の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 接続領域において、少なくとも1つの、任意に選択された複数の、または、すべての、以下の隣接する材料ペア、すなわち
導体/絶縁体、
絶縁体/導体、
絶縁体/絶縁体、および/または、
導体/導体、
が存在し、前記第1の接続層(32)の材料が斜線の左側に示され、前記第2の接続層(34)の材料が斜線の右側に示される、
請求項1〜11の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記第1の接続層(32)の第1の境界面(321)および前記第2の接続層(341)の第2の境界面(341)は、前記それぞれの接続領域で互いに隣接し、前記第1の境界面および/または前記第2の境界面は、少なくとも前記それぞれの接続領域において、あるいは、より大きなエリアにわたって、例えば、表面全体にわたって、1nm以下、好ましくは、0.5nm以下であるRMS粗さを含む、
請求項1〜12の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記半導体ボディ(10a、10b、10c)は、第1の半導体ボディであり、前記デバイス(50)は、光学的活性領域(12)を有する第2の半導体ボディ(10a、10b、10c)を含み、前記接続層ペア(30a、30b、30c)は、前記第1の半導体ボディと第2の半導体ボディとの間に配設されており、前記第1および第2の半導体ボディは、前記接続層ペアを介して互いに導電接続されている、
請求項1〜13の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - 前記第1の半導体ボディ(10a、10b、10c)の接続導体(74)は、前記半導体ボディ内でそれから電気的に絶縁されて前記第1の半導体ボディ全体を通って延びて、前記第2の半導体ボディに導電接続されており、前記接続導体と前記第2の半導体ボディとの間の前記導電接続の一部分は、前記半導体ボディ間に配設される前記接続層ペア(30b、30c)によって形成されている、
請求項14に記載のオプトエレクトロニクスデバイス。 - 前記デバイス(50)の前記それぞれの半導体ボディ(10a、10b、10c)を駆動するための1つまたは複数の電子要素(62、64、66、68)は、前記キャリア(60)に一体化されている、
請求項1〜15の少なくとも一項に記載のオプトエレクトロニクスデバイス。 - オプトエレクトロニクスデバイスを製造するための方法であって、
a)光学的活性領域(12)を有する半導体積層体(10)を設けるステップと、
b)前記半導体積層体および第1の接続層(32)が第1の複合体(100)を形成するように、前記第1の接続層(32)を前記半導体積層体に被着するステップと、
c)複合体要素(40、60、10)を設けるステップと、
d)前記複合体要素および第2の接続層が第2の複合体(200)を形成するように、前記第2の接続層(34)を前記複合体要素に被着するステップと、
e)前記第1および第2の接続層を介して直接接合によって前記第1および第2の複合体を接続するステップと、を含み、前記第1の接続層および前記第2の接続層から選択された少なくとも1つの層が放射透過性および導電性の酸化物を含有する、
方法。 - 前記第1の接続層(32)および/または前記第2の接続層(34)は、被着後、ステップe)前に、第1の温度で温度処理を受ける、
請求項17に記載の方法。 - 前記第1の接続層(32)および/または前記第2の接続層(34)は、プラズマプロセスを用いて前記温度処理後のステップe)で直接接合するために準備される、
請求項18に記載の方法。 - 前記第1の接続層(32)および前記第2の接続層(34)は、ステップe)の前記直接接合後に、前記第1の温度よりも低い第2の温度で温度処理を受ける、
請求項19に記載の方法。
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Also Published As
Publication number | Publication date |
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KR102214928B1 (ko) | 2021-02-09 |
TWI642208B (zh) | 2018-11-21 |
KR20180121614A (ko) | 2018-11-07 |
JP6850301B2 (ja) | 2021-03-31 |
US10686099B2 (en) | 2020-06-16 |
WO2017153123A1 (de) | 2017-09-14 |
TW201803156A (zh) | 2018-01-16 |
US20190097088A1 (en) | 2019-03-28 |
DE102016104280A1 (de) | 2017-09-14 |
CN108780826B (zh) | 2021-07-13 |
CN108780826A (zh) | 2018-11-09 |
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