JP2019216141A5 - - Google Patents

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Publication number
JP2019216141A5
JP2019216141A5 JP2018111171A JP2018111171A JP2019216141A5 JP 2019216141 A5 JP2019216141 A5 JP 2019216141A5 JP 2018111171 A JP2018111171 A JP 2018111171A JP 2018111171 A JP2018111171 A JP 2018111171A JP 2019216141 A5 JP2019216141 A5 JP 2019216141A5
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JP
Japan
Prior art keywords
insulating layer
opening
layer
wiring
reinforcing material
Prior art date
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Application number
JP2018111171A
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English (en)
Japanese (ja)
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JP7221601B2 (ja
JP2019216141A (ja
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Priority to JP2018111171A priority Critical patent/JP7221601B2/ja
Priority claimed from JP2018111171A external-priority patent/JP7221601B2/ja
Priority to US16/432,035 priority patent/US10542625B2/en
Publication of JP2019216141A publication Critical patent/JP2019216141A/ja
Publication of JP2019216141A5 publication Critical patent/JP2019216141A5/ja
Application granted granted Critical
Publication of JP7221601B2 publication Critical patent/JP7221601B2/ja
Active legal-status Critical Current
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JP2018111171A 2018-06-11 2018-06-11 配線基板、配線基板の製造方法 Active JP7221601B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018111171A JP7221601B2 (ja) 2018-06-11 2018-06-11 配線基板、配線基板の製造方法
US16/432,035 US10542625B2 (en) 2018-06-11 2019-06-05 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018111171A JP7221601B2 (ja) 2018-06-11 2018-06-11 配線基板、配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2019216141A JP2019216141A (ja) 2019-12-19
JP2019216141A5 true JP2019216141A5 (https=) 2021-04-01
JP7221601B2 JP7221601B2 (ja) 2023-02-14

Family

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Family Applications (1)

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JP2018111171A Active JP7221601B2 (ja) 2018-06-11 2018-06-11 配線基板、配線基板の製造方法

Country Status (2)

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US (1) US10542625B2 (https=)
JP (1) JP7221601B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY202414A (en) 2018-11-28 2024-04-27 Intel Corp Embedded reference layers fo semiconductor package substrates
JP7031088B1 (ja) * 2020-05-28 2022-03-07 京セラ株式会社 配線基板
KR20220151431A (ko) * 2021-05-06 2022-11-15 삼성전기주식회사 인쇄회로기판
US20230317592A1 (en) * 2022-04-01 2023-10-05 Intel Corporation Substrate with low-permittivity core and buildup layers

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4067604B2 (ja) * 1997-08-20 2008-03-26 松下電器産業株式会社 回路形成基板および回路形成基板の製造方法
JP2004207522A (ja) 2002-12-25 2004-07-22 Kyocera Corp 配線基板の製造方法
JP4054269B2 (ja) * 2003-03-20 2008-02-27 Ｔｄｋ株式会社 電子部品の製造方法および電子部品
EP1653789A4 (en) 2003-07-30 2008-09-24 Ibm PRINTED BOARD AND PROCESS FOR PRODUCING THE SAME
JP4776247B2 (ja) * 2005-02-09 2011-09-21 富士通株式会社 配線基板及びその製造方法
JP4855753B2 (ja) 2005-10-03 2012-01-18 富士通株式会社 多層配線基板及びその製造方法
JP5284147B2 (ja) * 2008-03-13 2013-09-11 日本特殊陶業株式会社 多層配線基板
JP5584986B2 (ja) 2009-03-25 2014-09-10 富士通株式会社 インターポーザ
US8974888B2 (en) * 2011-08-30 2015-03-10 International Business Machines Corporation Preventing conductive anodic filament (CAF) formation by sealing discontinuities in glass fiber bundles
JP2013149941A (ja) 2011-12-22 2013-08-01 Ngk Spark Plug Co Ltd 多層配線基板及びその製造方法
JP2013229526A (ja) * 2012-04-26 2013-11-07 Ngk Spark Plug Co Ltd 多層配線基板及びその製造方法
JP6532750B2 (ja) 2015-02-10 2019-06-19 新光電気工業株式会社 配線基板及びその製造方法

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