JP2019054169A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2019054169A
JP2019054169A JP2017178413A JP2017178413A JP2019054169A JP 2019054169 A JP2019054169 A JP 2019054169A JP 2017178413 A JP2017178413 A JP 2017178413A JP 2017178413 A JP2017178413 A JP 2017178413A JP 2019054169 A JP2019054169 A JP 2019054169A
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JP
Japan
Prior art keywords
region
semiconductor
type
semiconductor region
type impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2017178413A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019054169A5 (enExample
Inventor
小野　昇太郎
Shotaro Ono
昇太郎 小野
浩史 大田
Hiroshi Ota
浩史 大田
尚生 一條
Hisao Ichijo
尚生 一條
浩明 山下
Hiroaki Yamashita
浩明 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to JP2017178413A priority Critical patent/JP2019054169A/ja
Priority to EP18157871.7A priority patent/EP3457440A1/en
Priority to US15/901,930 priority patent/US20190088738A1/en
Priority to CN201810181613.8A priority patent/CN109509783A/zh
Publication of JP2019054169A publication Critical patent/JP2019054169A/ja
Publication of JP2019054169A5 publication Critical patent/JP2019054169A5/ja
Priority to US16/710,544 priority patent/US20200119142A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
JP2017178413A 2017-09-15 2017-09-15 半導体装置 Abandoned JP2019054169A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2017178413A JP2019054169A (ja) 2017-09-15 2017-09-15 半導体装置
EP18157871.7A EP3457440A1 (en) 2017-09-15 2018-02-21 Semiconductor device
US15/901,930 US20190088738A1 (en) 2017-09-15 2018-02-22 Semiconductor device
CN201810181613.8A CN109509783A (zh) 2017-09-15 2018-03-06 半导体装置
US16/710,544 US20200119142A1 (en) 2017-09-15 2019-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017178413A JP2019054169A (ja) 2017-09-15 2017-09-15 半導体装置

Publications (2)

Publication Number Publication Date
JP2019054169A true JP2019054169A (ja) 2019-04-04
JP2019054169A5 JP2019054169A5 (enExample) 2019-09-19

Family

ID=61256686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017178413A Abandoned JP2019054169A (ja) 2017-09-15 2017-09-15 半導体装置

Country Status (4)

Country Link
US (2) US20190088738A1 (enExample)
EP (1) EP3457440A1 (enExample)
JP (1) JP2019054169A (enExample)
CN (1) CN109509783A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024052952A1 (ja) * 2022-09-05 2024-03-14 三菱電機株式会社 半導体装置、半導体装置の制御方法、および半導体装置の製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6981890B2 (ja) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置
CN112993007B (zh) * 2019-12-13 2025-01-14 南通尚阳通集成电路有限公司 超结结构及超结器件
CN115566038B (zh) * 2021-07-01 2025-09-26 深圳尚阳通科技股份有限公司 超结器件及其制造方法
CN116137283B (zh) * 2021-11-17 2025-09-12 苏州东微半导体股份有限公司 半导体超结功率器件

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115589A (ja) * 2001-10-03 2003-04-18 Fuji Electric Co Ltd 半導体装置及びその製造方法
JP2005019528A (ja) * 2003-06-24 2005-01-20 Toyota Central Res & Dev Lab Inc 半導体装置とその製造方法
JP2006073987A (ja) * 2004-08-04 2006-03-16 Fuji Electric Device Technology Co Ltd 半導体素子
JP2006179598A (ja) * 2004-12-21 2006-07-06 Toshiba Corp 電力用半導体装置
JP2007251023A (ja) * 2006-03-17 2007-09-27 Toyota Motor Corp スーパージャンクション構造を有する半導体装置とその製造方法
JP2007300034A (ja) * 2006-05-02 2007-11-15 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2008258442A (ja) * 2007-04-05 2008-10-23 Toshiba Corp 電力用半導体素子
JP2009272397A (ja) * 2008-05-02 2009-11-19 Toshiba Corp 半導体装置
WO2011093473A1 (ja) * 2010-01-29 2011-08-04 富士電機システムズ株式会社 半導体装置
JP2015213141A (ja) * 2014-04-17 2015-11-26 富士電機株式会社 縦型半導体装置およびその製造方法
US20160064478A1 (en) * 2014-09-01 2016-03-03 Silergy Semiconductor Technology (Hangzhou) Ltd. Super-junction structure and method for manufacturing the same and semiconductor device thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3940518B2 (ja) * 1999-03-10 2007-07-04 株式会社東芝 高耐圧半導体素子
JP3973395B2 (ja) * 2001-10-16 2007-09-12 株式会社豊田中央研究所 半導体装置とその製造方法
JP5484741B2 (ja) * 2009-01-23 2014-05-07 株式会社東芝 半導体装置
DE102016113129B3 (de) * 2016-07-15 2017-11-09 Infineon Technologies Ag Halbleitervorrichtung, die eine Superjunction-Struktur in einem SiC-Halbleiterkörper enthält

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115589A (ja) * 2001-10-03 2003-04-18 Fuji Electric Co Ltd 半導体装置及びその製造方法
JP2005019528A (ja) * 2003-06-24 2005-01-20 Toyota Central Res & Dev Lab Inc 半導体装置とその製造方法
JP2006073987A (ja) * 2004-08-04 2006-03-16 Fuji Electric Device Technology Co Ltd 半導体素子
JP2006179598A (ja) * 2004-12-21 2006-07-06 Toshiba Corp 電力用半導体装置
JP2007251023A (ja) * 2006-03-17 2007-09-27 Toyota Motor Corp スーパージャンクション構造を有する半導体装置とその製造方法
JP2007300034A (ja) * 2006-05-02 2007-11-15 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2008258442A (ja) * 2007-04-05 2008-10-23 Toshiba Corp 電力用半導体素子
JP2009272397A (ja) * 2008-05-02 2009-11-19 Toshiba Corp 半導体装置
WO2011093473A1 (ja) * 2010-01-29 2011-08-04 富士電機システムズ株式会社 半導体装置
JP2015213141A (ja) * 2014-04-17 2015-11-26 富士電機株式会社 縦型半導体装置およびその製造方法
US20160064478A1 (en) * 2014-09-01 2016-03-03 Silergy Semiconductor Technology (Hangzhou) Ltd. Super-junction structure and method for manufacturing the same and semiconductor device thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024052952A1 (ja) * 2022-09-05 2024-03-14 三菱電機株式会社 半導体装置、半導体装置の制御方法、および半導体装置の製造方法
JPWO2024052952A1 (enExample) * 2022-09-05 2024-03-14

Also Published As

Publication number Publication date
US20200119142A1 (en) 2020-04-16
US20190088738A1 (en) 2019-03-21
EP3457440A1 (en) 2019-03-20
CN109509783A (zh) 2019-03-22

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