JP2019054155A - 半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法 - Google Patents
半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法 Download PDFInfo
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- JP2019054155A JP2019054155A JP2017178268A JP2017178268A JP2019054155A JP 2019054155 A JP2019054155 A JP 2019054155A JP 2017178268 A JP2017178268 A JP 2017178268A JP 2017178268 A JP2017178268 A JP 2017178268A JP 2019054155 A JP2019054155 A JP 2019054155A
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Abstract
Description
先ず、本実施形態に係る集積回路装置について説明する。
図1は、本実施形態に係る集積回路装置を示す平面図である。
図2は、本実施形態に係る集積回路装置を示す一部拡大断面図である。
なお、各図は模式的なものであり、適宜誇張及び省略して描かれている。例えば、各構成要素は実際よりも少なく且つ大きく描かれている。また、図間において、構成要素の数及び寸法比等は、必ずしも一致していない。
図3は、本実施形態に係る半導体チップを示す平面図である。
図4は、本実施形態に係る半導体チップを示す一部拡大断面図である。
以下に説明する半導体チップ10は、支持基板11上に搭載され、接続部材12によって他の半導体チップに接続される前の状態である。
図5〜図20は、本実施形態に係る半導体チップの製造方法を示す断面図である。
図21は、本実施形態に係る集積回路装置の製造方法を示す断面図である。
図21に示すように、支持基板11上に半導体チップ10A〜10Cを搭載する。なお、図21には、半導体チップ10A及び10Bのみを示している。このとき、隣り合う半導体チップ10の半田層45が、相互に対向するように配置する。半導体チップ10A〜10Cは、それぞれ、上述の図5〜図20に示す工程によって製造されたものであるが、相互に異なるライン又はタイミングで製造された異なる種類の半導体チップである。
本実施形態においては、半導体チップ10の側面にパッド40を形成し、パッド40の側面上に半田層45を形成し、半田層45の先端をシリコン基板20及び配線層21の側面よりも側方に突出させている。これにより、支持基板11上に複数の半導体チップ10を搭載し、半田層45を一旦溶融させて凝固させることにより、対向する一対の半田層45が一体的な接続部材12となり、隣り合う半導体チップ10のパッド40同士を接続することができる。
10、10A、10B、10C:半導体チップ
11:支持基板
12:接続部材
20:シリコン基板
20u:下面
20w:シリコンウェーハ
21:配線層
22、23、24:層間絶縁膜
25:トランジスタ
26:不純物含有層
27:ゲート絶縁膜
28:ゲート電極
30:ビア
31:配線
35:エッチングストッパ層
36:絶縁膜
37:積層体
38:絶縁膜
39:ビアホール
40:パッド
40a:上面
40b:側面
40c:上面
40f:金属膜
40s:拡散防止層
40t:本体部
41:パッシベーション膜
42:シリコン酸化膜
43:シリコン窒化膜
45:半田層
51:レジスト膜
51a:開口部
52:溝
53:レジスト膜
53a:開口部
54:レジスト膜
55:レジスト膜
55a:開口部
56:レジスト膜
56a:開口部
57:溝
Rc:チップ領域
Rd:ダイシング領域
Claims (6)
- 半導体基板と、
前記半導体基板上に設けられた配線層と、
前記配線層の側面上に設けられたパッドと、
前記パッドの側面に接し、前記半導体基板の側面及び前記配線層の側面よりも側方に突出した半田層と、
を備えた半導体チップ。 - 前記パッドは前記配線層の上面上にも配置されており、
前記半田層は前記パッドの上面にも接している請求項1記載の半導体チップ。 - 支持基板と、
前記支持基板上に設けられた第1半導体チップ及び第2半導体チップと、
半田からなる接続部材と、
を備え、
前記第1半導体チップ及び前記第2半導体チップは、それぞれ、
半導体基板と、
前記半導体基板上に設けられた配線層と、
前記配線層の側面上に設けられたパッドと、
を有し、
前記接続部材は、前記第1半導体チップの前記パッドの側面と、前記第2半導体チップの前記パッドの側面に接した集積回路装置。 - 前記第1半導体チップ及び前記第2半導体チップにおいて、前記パッドは前記配線層の上面上にも配置されており、
前記接続部材は、前記第1半導体チップの前記パッドの上面及び前記第2半導体チップの前記パッドの上面にも接した請求項3記載の集積回路装置。 - 半導体基板上に配線層を形成する工程と、
前記配線層に第1溝を形成することにより、前記配線層を複数の部分に分割する工程と、
前記第1溝の内面上に金属膜を形成する工程と、
前記第1溝の底面に第2溝を形成することにより、前記金属膜を複数のパッドに分割する工程と、
前記第1溝の両側面上に、前記第2溝の直上域まで突出し、且つ、相互に接触しないように、半田層を形成する工程と、
前記半導体基板の下面を前記第2溝まで研削することにより、前記半導体基板を複数の部分に分割する工程と、
を備えた半導体チップの製造方法。 - 支持基板上に、第1半導体基板、前記第1半導体基板上に設けられた第1配線層、前記第1配線層の側面上に設けられた第1パッド、及び、前記第1パッドの側面に接し、前記第1半導体基板の側面及び前記第1配線層の側面よりも側方に突出した第1半田層を含む第1半導体チップ、並びに、第2半導体基板、前記第2半導体基板上に設けられた第2配線層、前記第2配線層の側面上に設けられた第2パッド、及び、前記第2パッドの側面に接し、前記第2半導体基板の側面及び前記第2配線層の側面よりも側方に突出した第2半田層を含む第2半導体チップを、前記第1半田層と前記第2半田層が対向するように搭載する工程と、
前記第1半田層及び前記第2半田層を加熱することにより、前記第1半田層及び前記第2半田層を一体化させる工程と、
を備えた集積回路装置の製造方法。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0778932A (ja) * | 1993-09-07 | 1995-03-20 | Toshiba Corp | 半導体装置の製造方法 |
JPH07169796A (ja) * | 1993-10-13 | 1995-07-04 | Yamaha Corp | 半導体装置とその製造方法 |
JP2001068513A (ja) * | 1999-08-30 | 2001-03-16 | Sharp Corp | 半導体装置 |
US6501663B1 (en) * | 2000-02-28 | 2002-12-31 | Hewlett Packard Company | Three-dimensional interconnect system |
JP2008182235A (ja) * | 2007-01-23 | 2008-08-07 | Samsung Electronics Co Ltd | 側面パッドを備えるチップ、その製造方法及びそのチップを利用したパッケージ |
US20090308641A1 (en) * | 2008-06-13 | 2009-12-17 | Dong-Joon Kim | Chip having side protection terminal and package using the chip |
WO2015049852A1 (ja) * | 2013-10-01 | 2015-04-09 | パナソニックIpマネジメント株式会社 | 半導体装置 |
US9209143B2 (en) * | 2013-09-26 | 2015-12-08 | Intel IP Corporation | Die edge side connection |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10209164A (ja) | 1997-01-23 | 1998-08-07 | Toyota Motor Corp | 半導体装置の製造方法 |
US6611050B1 (en) * | 2000-03-30 | 2003-08-26 | International Business Machines Corporation | Chip edge interconnect apparatus and method |
JP2003188263A (ja) | 2001-12-17 | 2003-07-04 | Sharp Corp | 半導体集積回路チップの製造方法とその半導体集積回路チップを用いた半導体パッケージ |
TWI282158B (en) * | 2002-10-11 | 2007-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with ground-enhancing chip and fabrication method thereof |
JP2004288816A (ja) * | 2003-03-20 | 2004-10-14 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
SG119185A1 (en) * | 2003-05-06 | 2006-02-28 | Micron Technology Inc | Method for packaging circuits and packaged circuits |
JP2006049699A (ja) | 2004-08-06 | 2006-02-16 | Canon Inc | 側面電極を有する半導体装置とその製造方法 |
US7271482B2 (en) * | 2004-12-30 | 2007-09-18 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7262134B2 (en) * | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
JP2007207906A (ja) | 2006-01-31 | 2007-08-16 | Toshiba Corp | 半導体集積回路および半導体集積回路の製造方法 |
US20100117224A1 (en) * | 2008-08-29 | 2010-05-13 | Vertical Circuits, Inc. | Sensor |
US20180018709A1 (en) * | 2016-05-31 | 2018-01-18 | Ramot At Tel-Aviv University Ltd. | Information spread in social networks through scheduling seeding methods |
US10199266B2 (en) * | 2016-12-26 | 2019-02-05 | Intel Corporation | Integrated circuit interconnect structure having metal oxide adhesive layer |
-
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- 2017-09-15 JP JP2017178268A patent/JP6836485B2/ja active Active
-
2018
- 2018-03-14 US US15/920,780 patent/US10658321B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0778932A (ja) * | 1993-09-07 | 1995-03-20 | Toshiba Corp | 半導体装置の製造方法 |
JPH07169796A (ja) * | 1993-10-13 | 1995-07-04 | Yamaha Corp | 半導体装置とその製造方法 |
JP2001068513A (ja) * | 1999-08-30 | 2001-03-16 | Sharp Corp | 半導体装置 |
US6501663B1 (en) * | 2000-02-28 | 2002-12-31 | Hewlett Packard Company | Three-dimensional interconnect system |
JP2008182235A (ja) * | 2007-01-23 | 2008-08-07 | Samsung Electronics Co Ltd | 側面パッドを備えるチップ、その製造方法及びそのチップを利用したパッケージ |
US20090308641A1 (en) * | 2008-06-13 | 2009-12-17 | Dong-Joon Kim | Chip having side protection terminal and package using the chip |
US9209143B2 (en) * | 2013-09-26 | 2015-12-08 | Intel IP Corporation | Die edge side connection |
WO2015049852A1 (ja) * | 2013-10-01 | 2015-04-09 | パナソニックIpマネジメント株式会社 | 半導体装置 |
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