JP2019054058A - 半導体パッケージおよびその製造方法 - Google Patents
半導体パッケージおよびその製造方法 Download PDFInfo
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- JP2019054058A JP2019054058A JP2017176057A JP2017176057A JP2019054058A JP 2019054058 A JP2019054058 A JP 2019054058A JP 2017176057 A JP2017176057 A JP 2017176057A JP 2017176057 A JP2017176057 A JP 2017176057A JP 2019054058 A JP2019054058 A JP 2019054058A
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- wiring
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- organic film
- solder resist
- opening
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 21
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 4
- -1 imidazole compound Chemical class 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000576 coating method Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11464—Electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
Description
Claims (7)
- 基板と、
前記基板上で互いに離れた端面を有し、銅を含んだ配線と、
前記配線上に設けられ、前記端面間に開口部を有するソルダーレジストと、
前記端面を覆う有機膜と、
を備える半導体パッケージ。 - 前記有機膜が、前記開口部から露出している、請求項1に記載の半導体パッケージ。
- 前記有機膜が、銅とイミダゾール化合物との錯体を含んでいる、請求項1または2に記載の半導体パッケージ。
- 前記基板下に半導体素子が設けられ、
前記配線が、前記半導体素子に入出力される信号を伝送する信号線である、請求項1から3のいずれかに記載の半導体パッケージ。 - 前記半導体素子が半導体メモリである、請求項4に記載の半導体パッケージ。
- 基板上に設けられた銅を含んだ配線上にソルダーレジストを形成し、
前記ソルダーレジストに開口部を形成し、
前記ソルダーレジストをマスクとして用いて前記開口部から露出している前記配線をエッチングし、
前記エッチングによって露出した前記配線の端面に有機膜を形成する、
半導体パッケージの製造方法。 - 前記ソルダーレジストに前記開口部を複数形成し、
一部の前記開口部に前記ソルダーレジストとは異種のレジストを塗布し、
前記レジストを前記マスクとして用いて前記配線をエッチングした後に前記レジストを剥離し、
前記一部の開口部から露出している前記配線の表面と、前記端面とに前記有機膜を無電解めっき処理により同時に形成する、請求項6に記載の半導体パッケージの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017176057A JP2019054058A (ja) | 2017-09-13 | 2017-09-13 | 半導体パッケージおよびその製造方法 |
US15/905,288 US20190081003A1 (en) | 2017-09-13 | 2018-02-26 | Semiconductor package and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017176057A JP2019054058A (ja) | 2017-09-13 | 2017-09-13 | 半導体パッケージおよびその製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2019054058A true JP2019054058A (ja) | 2019-04-04 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2017176057A Pending JP2019054058A (ja) | 2017-09-13 | 2017-09-13 | 半導体パッケージおよびその製造方法 |
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US (1) | US20190081003A1 (ja) |
JP (1) | JP2019054058A (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06237069A (ja) * | 1993-02-12 | 1994-08-23 | Nec Corp | 印刷配線板の製造方法 |
JP2013069019A (ja) * | 2011-09-21 | 2013-04-18 | Toshiba Corp | 半導体メモリカード及びその製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102462505B1 (ko) * | 2016-04-22 | 2022-11-02 | 삼성전자주식회사 | 인쇄회로기판 및 반도체 패키지 |
-
2017
- 2017-09-13 JP JP2017176057A patent/JP2019054058A/ja active Pending
-
2018
- 2018-02-26 US US15/905,288 patent/US20190081003A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06237069A (ja) * | 1993-02-12 | 1994-08-23 | Nec Corp | 印刷配線板の製造方法 |
JP2013069019A (ja) * | 2011-09-21 | 2013-04-18 | Toshiba Corp | 半導体メモリカード及びその製造方法 |
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US20190081003A1 (en) | 2019-03-14 |
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