JP2018534766A - 静電気放電保護デバイス及び回路装置 - Google Patents
静電気放電保護デバイス及び回路装置 Download PDFInfo
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- JP2018534766A JP2018534766A JP2018515490A JP2018515490A JP2018534766A JP 2018534766 A JP2018534766 A JP 2018534766A JP 2018515490 A JP2018515490 A JP 2018515490A JP 2018515490 A JP2018515490 A JP 2018515490A JP 2018534766 A JP2018534766 A JP 2018534766A
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- 238000001514 detection method Methods 0.000 claims abstract description 44
- 101150021503 Mesd gene Proteins 0.000 claims abstract description 38
- 230000000630 rising effect Effects 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 230000007704 transition Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
V1=VPAD[R2/(R1+R2)] 式1
ここで、VPADは高電圧給電端子HV_PADにおける電圧レベルである。
Vesd=Vtrans*(R1+R2)/R2 式2
ここで、Vesdは電圧のしきい値であり、Vtransは第1のインバータの遷移電圧である。検出回路30の電圧のしきい値は、例えば、電圧分圧器のため1つ以上の可変抵抗素子を用いることで、構成されてもよい。
5 保護すべき回路
10 ESD保護デバイス
20 制御回路
30 検出回路
40 キャパシタ回路
D ドレイン
Dpar1、Dpar2 寄生ダイオード
ESD_neg 負のESD保護部分
ESD_pos 正のESD保護部分
G ゲート
GND 基準電位端子
HV_PAD 高電圧給電端子
M1、M3 第2のトランジスタ
M2、M4 第1のトランジスタ
Mesd トランジスタ
NMOS_1 低電圧Nチャネル金属―酸化膜―半導体の電界効果トランジスタ
NMOS_2 低電圧Nチャネル金属―酸化膜―半導体の電界効果トランジスタ
R1、R2 第1の抵抗素子、第2の抵抗素子
R3 制御回路の抵抗器
S ソース
SUB 基板
V1 検出回路の入力電圧
VDD 給電電圧
VPAD 高電圧給電端子の電圧レベル
Claims (12)
- 保護すべき回路(5)の少なくとも一つの高電圧給電端子(HV_PAD)に接続可能な静電気放電(ESD)保護デバイス(10)であって、
検出回路(30)、制御回路(20)及びトランジスタ(Mesd)を備え、
前記検出回路(30)は、正のESD事象と前記高電圧給電端子(HV_PAD)上の高電圧パッドパルスの立ち上がりとを区別するように、配置されるとともに構成され、
前記制御回路(20)は、前記検出回路(30)の検出出力信号に依存して、その出力に制御信号を供給するように構成され、
前記トランジスタ(Mesd)は、基準電位端子(GND)と前記高電圧給電端子(HV_PAD)に接続され、前記トランジスタ(Mesd)の制御入力は前記制御回路(20)の出力に接続される、
ESD保護デバイス(10)。 - 前記ESD保護デバイス(10)は、前記高電圧給電端子(HV_PAD)を前記検出回路(30)の入力へ、AC結合又はハイパス結合するための、キャパシタ回路(40)を備える、請求項1に記載のESD保護デバイス(10)。
- 前記検出回路(30)は、前記検出回路(30)の入力信号が所定のしきい値を超えたときに、ESD事象を検出するように構成された、しきい値検出回路を備える、
請求項1又は2に記載のESD保護デバイス(10)。 - 前記検出回路(30)の前記しきい値は、設定可能である、
請求項3に記載のESD保護デバイス(10)。 - 前記しきい値検出回路は、コンパレータを備えている、
請求項3乃至4のいずれか一項に記載のESD保護デバイス(10)。 - 前記コンパレータは、電圧分圧器及び第1のインバータを備え、
前記電圧分圧器は前記キャパシタ回路(40)に直列に接続され、前記第1のインバータの入力は部分電圧を取り出すための前記電圧分圧器に接続される、
請求項5に記載のESD保護デバイス(10)。 - 前記検出回路(30)は、能動部品としてはトランジスタのみを備える、
請求項1乃至6のいずれか一項に記載のESD保護デバイス(10)。 - 前記制御回路(20)は、第2のインバータを備える、
請求項1乃至7のいずれか一項に記載のESD保護デバイス(10)。 - 前記トランジスタ(Mesd)は、直列に接続された2つの低電圧Nチャネル金属―酸化膜―半導体の電界効果トランジスタ、NMOS_1及びNMOS_2を備える、
請求項1乃至8のいずれか一項に記載のESD保護デバイス(10)。 - 前記トランジスタ(Mesd)は、直列に接続された2つの低電圧Nチャネル金属―酸化膜―半導体の電界効果トランジスタ、NMOS_1及びNMOS_2を備え、それぞれのトランジスタは各々ディープNウェル内に配置される、
請求項1乃至8のいずれか一項に記載のESD保護デバイス(10)。 - 前記トランジスタ(Mesd)は、高電圧Nウェル及びPウェルを備える高電圧Nチャネル金属―酸化膜―半導体の電界効果トランジスタを備える、
請求項1乃至8のいずれか一項に記載のESD保護デバイス(10)。 - 請求項1乃至11のいずれか一項に記載の前記ESD保護デバイス(10)と、プログラム可能デバイスと、を備え、前記ESD保護デバイス(10)は、前記プログラム可能デバイスの高電圧給電端子(HV_PAD)に接続される、
回路装置(1)。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2015/072449 WO2017054849A1 (en) | 2015-09-29 | 2015-09-29 | Electrostatic discharge protection device and circuit apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018534766A true JP2018534766A (ja) | 2018-11-22 |
JP6708989B2 JP6708989B2 (ja) | 2020-06-10 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2018515490A Expired - Fee Related JP6708989B2 (ja) | 2015-09-29 | 2015-09-29 | 静電気放電保護デバイス及び回路装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20180287377A1 (ja) |
EP (1) | EP3357090B1 (ja) |
JP (1) | JP6708989B2 (ja) |
CN (1) | CN108028251B (ja) |
WO (1) | WO2017054849A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108834011B (zh) * | 2018-05-30 | 2020-08-11 | 出门问问信息科技有限公司 | 一种对麦克风进行静电防护的方法及装置 |
TWI654733B (zh) * | 2018-06-04 | 2019-03-21 | 茂達電子股份有限公司 | 靜電放電保護電路 |
CN109449156B (zh) * | 2018-12-20 | 2024-03-22 | 上海艾为电子技术股份有限公司 | 一种端口静电释放保护电路 |
CN110212507B (zh) * | 2019-05-23 | 2021-06-18 | 上海艾为电子技术股份有限公司 | 浪涌保护电路 |
US11296502B2 (en) * | 2020-07-22 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company Limited | Electrostatic discharge protection circuit |
US11355927B2 (en) * | 2020-07-22 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for operating the same |
TWI784502B (zh) * | 2021-04-29 | 2022-11-21 | 華邦電子股份有限公司 | 靜電放電防護電路 |
TWI795068B (zh) * | 2021-11-11 | 2023-03-01 | 世界先進積體電路股份有限公司 | 靜電放電保護電路 |
US11811222B2 (en) | 2021-12-16 | 2023-11-07 | Vanguard International Semiconductor Corporation | Electrostatic discharge protection circuit |
CN114597856B (zh) * | 2022-03-25 | 2023-07-25 | 歌尔微电子股份有限公司 | 传感器麦克风及其内置校准电路的保护电路、方法 |
Family Cites Families (11)
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US5959820A (en) * | 1998-04-23 | 1999-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cascode LVTSCR and ESD protection circuit |
TW511271B (en) * | 2001-10-19 | 2002-11-21 | Winbond Electronics Corp | Electrostatic discharge protection circuit with high electrostatic discharge tolerance capability |
US7027276B2 (en) * | 2004-04-21 | 2006-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage ESD protection circuit with low voltage transistors |
US7660086B2 (en) * | 2006-06-08 | 2010-02-09 | Cypress Semiconductor Corporation | Programmable electrostatic discharge (ESD) protection device |
US7804669B2 (en) * | 2007-04-19 | 2010-09-28 | Qualcomm Incorporated | Stacked ESD protection circuit having reduced trigger voltage |
DE102008006963B4 (de) * | 2008-01-31 | 2015-07-30 | Globalfoundries Inc. | ESD-Leistungsklemmeinrichtung mit stabiler Einschaltfunktion |
US8238067B2 (en) * | 2008-12-11 | 2012-08-07 | Ati Technologies Ulc | Electrostatic discharge circuit and method |
TWI416836B (zh) * | 2010-06-29 | 2013-11-21 | Realtek Semiconductor Corp | 靜電防護電路 |
US8649137B2 (en) * | 2011-10-20 | 2014-02-11 | Semiconductor Components Industries, Llc | Semiconductor device and method of forming same for ESD protection |
DE112013006080T5 (de) * | 2012-12-19 | 2015-08-27 | Knowles Electronics, Llc | Vorrichtung und Verfahren für einen Hochspannungs-E/A-Elektrostatikentladungsschutz |
JP2016111186A (ja) * | 2014-12-05 | 2016-06-20 | ソニー株式会社 | 半導体集積回路 |
-
2015
- 2015-09-29 US US15/764,872 patent/US20180287377A1/en not_active Abandoned
- 2015-09-29 WO PCT/EP2015/072449 patent/WO2017054849A1/en active Application Filing
- 2015-09-29 CN CN201580083467.XA patent/CN108028251B/zh active Active
- 2015-09-29 EP EP15771590.5A patent/EP3357090B1/en active Active
- 2015-09-29 JP JP2018515490A patent/JP6708989B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20180287377A1 (en) | 2018-10-04 |
CN108028251B (zh) | 2022-03-08 |
CN108028251A (zh) | 2018-05-11 |
EP3357090A1 (en) | 2018-08-08 |
WO2017054849A1 (en) | 2017-04-06 |
EP3357090B1 (en) | 2020-06-17 |
JP6708989B2 (ja) | 2020-06-10 |
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