JP2018523924A - ダミーゲートを用いないパターニング方法 - Google Patents
ダミーゲートを用いないパターニング方法 Download PDFInfo
- Publication number
- JP2018523924A JP2018523924A JP2018506291A JP2018506291A JP2018523924A JP 2018523924 A JP2018523924 A JP 2018523924A JP 2018506291 A JP2018506291 A JP 2018506291A JP 2018506291 A JP2018506291 A JP 2018506291A JP 2018523924 A JP2018523924 A JP 2018523924A
- Authority
- JP
- Japan
- Prior art keywords
- uncovered
- fin
- gate
- gate structure
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000000059 patterning Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000003989 dielectric material Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000002070 nanowire Substances 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000011161 development Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 abstract description 13
- 239000002131 composite material Substances 0.000 abstract 1
- 238000013461 design Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
トレンチを画定するエッチングマスクおよび材料は、覆われていないフィン部分を除去するための複合エッチングマスクを提供する。 その後、トレンチセグメントは誘電体材料で充填される。
ダミーゲートペアが必要でなければ、所与の基板は単位面積当たり顕著により多くの電気デバイスに適合することができる。
Description
本出願は、2015年8月7日に出願された、米国仮出願特許第62/202,599号、発明の名称「Method
of Patterning with Single Diffusion Cuts」の利益を主張するものであり、その開示内容全体は参照により本願に組み込まれる。
従来の製造技術においては、例えばロジックセルのセルレイアウトに関して、フィン又はワイヤが最初に比較的長く作製され、後に特定の場所で切断される。そのようなフィーチャを、フォトリソグラフィシステムの解像度以下にフィーチャサイズを縮小するダブルパターニング技術を使用することによって作製することができる。フォトリソグラフィシステムによって作製されたエッチングマスクは、規定の許容範囲内で材料を正確に切断又は除去するための十分な解像度を有していないので、そのような比較的小さいフィーチャの切断は問題になることがある。そのような従来のエッチングマスクを使用することによって、不十分なデバイス性能又はデバイス欠陥が生じる可能性がある。
本明細書における技術は、精度を保証するためのダミーゲートペアを必要とすることなく、フィン及びナノワイヤのための正確な切断を提供する。本明細書における技術は、ゲート構造が開口されるまで、フィンを切断されないままにすることを含み、その後に、1つの開口されたゲート構造が、切断の配置に集中するために使用される。包囲する誘電材料が、特定の場所において切断が行われることを保証するために、エッチングマスクの一部として使用される。ゲートスペーサ材料に対して選択的なエッチングを行うことによって、覆われていないフィン(その上に形成されているエッチングマスクによってさらに画定されている)を、ゲート構造によって以前占有されていた空間の内側/空間内でエッチングすることができる。覆われていないフィンをエッチングした後に、空間を誘電材料によって充填することができる。そのような充填誘電材料を、所定の場所に残存させることができ、その結果、ゲート構造によって以前占有されていた空間は金属化されないが、しかしながら誘電体として残存する。このことは、デバイスに残される金属化されたダミーゲートは存在しないこと、またダミーゲートペアをセル内に設計する必要がないことを意味している。従って、本明細書に記載する技術によって、単なる補償エッチングマスクとしての2つのダミーゲートを使用することはもはや必要なくなり、このことは所定のセルにおけるより多くの実際の空間を機能デバイスのために使用でき、それによってデバイス密度が高まることを意味している。
Claims (14)
- 基板をパターニングするための方法において、
前記方法は、
基板の加工面にフィン構造のアレイを形成するステップと、
前記基板の前記加工面にゲート構造のアレイを形成するステップであって、前記ゲート構造のアレイは、前記フィン構造のアレイのフィン構造の一部に交差して覆うゲート構造を有し、さらに前記ゲート構造の側壁に接し且つ前記フィン構造の残余部分を覆う第1誘電材料を含む、ステップと、
前記ゲート構造の部分を覆わない第1エッチングマスクを前記基板上に形成するステップと、
前記第1エッチングマスクによって覆われていない前記ゲート構造の部分を除去するステップであって、それによって、前記第1誘電材料によって画定されたトレンチ区分を形成し、前記トレンチ区分内に、前記フィン構造の覆われていない部分が存在する、ステップと、
前記トレンチ区分から、覆われていないフィン構造を除去するステップと、
前記トレンチ区分を、第2誘電材料によって充填するステップと、
を含む、基板をパターニングするための方法。 - 覆われていない前記ゲート構造の部分を除去するステップは、前記第1エッチングマスクに対して覆われていない前記ゲート構造の部分をエッチングする第1エッチング処理を実行するステップを含む、請求項1記載の方法。
- 前記覆われていないフィン構造を除去するステップは、前記ゲート構造の材料に関して前記フィン構造の材料をエッチングする第2エッチング処理を実行するステップを含む、請求項1記載の方法。
- 前記フィン構造は、保護膜を含み、
またさらに、前記覆われていないフィン構造を除去するステップに先行して、前記覆われていないフィン構造から前記保護膜を除去するステップを含む、請求項3記載の方法。 - 前記第2エッチング処理を実行するステップは、前記トレンチ区分の側壁を過ぎて、前記覆われていないフィン構造に横方向に凹部を形成する等方性エッチングを実行することを含む、請求項3記載の方法。
- 前記トレンチ区分を前記第2誘電材料によって充填するステップは、過剰量の誘電材料を堆積させて、前記ゲート構造の上面まで前記基板を平坦化するステップを含む、請求項1記載の方法。
- 前記フィン構造は、相互に平行な前記フィン構造を備えた下地層の上に延在する一連の線形の構造を含む、請求項1記載の方法。
- 前記ゲート構造は、下地層の上に延在する一連の線形の構造を含み、且つ前記フィン構造に垂直に交差する、請求項1記載の方法。
- 前記第1エッチングマスクは、フォトレジスト膜のフォトリソグラフィ露光及び現像によって形成される、請求項1記載の方法。
- 基板をパターニングするための方法において、
前記方法は、
基板の加工面にナノワイヤ構造のアレイを形成するステップと、
前記基板の前記加工面にゲート構造のアレイを形成するステップであって、前記ゲート構造のアレイは、前記ナノワイヤ構造の一部に交差して覆うゲート構造を有し、さらに前記ゲート構造の側壁に接し、且つ前記ナノワイヤ構造の残余部分を覆う第1誘電材料を含む、ステップと、
前記ゲート構造の部分を覆わない第1エッチングマスクを前記基板上に形成すること、
前記第1エッチングマスクによって覆われていない前記ゲート構造の部分を除去するステップであって、それによって、前記第1誘電材料によって画定された開放空間を形成し、前記開放空間内に、前記ナノワイヤ構造の覆われていない部分が存在する、ステップと、
前記開放空間から、覆われていないナノワイヤ構造を除去するステップと、
前記開放空間を、第2誘電材料によって充填するステップと、
を含む、基板をパターニングするための方法。 - 覆われていない前記ゲート構造の部分を除去するステップは、前記第1エッチングマスクに対して覆われていない前記ゲート構造の前記部分をエッチングする第1エッチング処理を実行するステップを含む、請求項10記載の方法。
- 前記覆われていないナノワイヤ構造を除去するステップは、前記ゲート構造の材料に関して前記ナノワイヤ構造の材料をエッチングする第2エッチング処理を実行するステップを含む、請求項10記載の方法。
- 前記ナノワイヤ構造は、保護膜を含み、
またさらに、前記覆われていないナノワイヤ構造を除去するステップに先行して、前記覆われていないナノワイヤ構造から前記保護膜を除去するステップを含む、請求項12記載の方法。 - 前記第2エッチング処理を実行するステップは、前記開放空間の側壁を過ぎて、前記覆われていないフィン構造に横方向に凹部を形成する等方性エッチングを実行するステップを含む、請求項12記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562202599P | 2015-08-07 | 2015-08-07 | |
US62/202,599 | 2015-08-07 | ||
PCT/US2016/044474 WO2017027224A1 (en) | 2015-08-07 | 2016-07-28 | Method of patterning without dummy gates |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018523924A true JP2018523924A (ja) | 2018-08-23 |
JP6630896B2 JP6630896B2 (ja) | 2020-01-15 |
Family
ID=57983462
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018506291A Active JP6630896B2 (ja) | 2015-08-07 | 2016-07-28 | ダミーゲートを用いないパターニング方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9721793B2 (ja) |
JP (1) | JP6630896B2 (ja) |
KR (1) | KR102545872B1 (ja) |
CN (1) | CN108028268B (ja) |
TW (1) | TWI594318B (ja) |
WO (1) | WO2017027224A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10056469B1 (en) * | 2017-02-13 | 2018-08-21 | Globalfoundries Inc. | Gate cut integration and related device |
KR102320047B1 (ko) | 2017-07-05 | 2021-11-01 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
WO2019035945A1 (en) | 2017-08-16 | 2019-02-21 | Tokyo Electron Limited | METHOD AND DEVICE FOR INCORPORATING SINGLE DIFFUSION BREAK IN NANOCANAL STRUCTURES OF FET DEVICES |
US10497778B2 (en) * | 2017-11-30 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10833078B2 (en) | 2017-12-04 | 2020-11-10 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
US10916478B2 (en) | 2018-02-20 | 2021-02-09 | Globalfoundries U.S. Inc. | Methods of performing fin cut etch processes for FinFET semiconductor devices |
US10629492B2 (en) | 2018-04-27 | 2020-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure having a dielectric gate and methods thereof |
US10580685B2 (en) | 2018-07-27 | 2020-03-03 | Globalfoundries Inc. | Integrated single diffusion break |
US10700204B2 (en) | 2018-08-17 | 2020-06-30 | Qualcomm Incorporated | Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods |
US10872971B1 (en) * | 2019-06-18 | 2020-12-22 | Semiconductor Manufacturing (Shanghai) International Corporation | Semiconductor structure and formation method thereof |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070018239A1 (en) * | 2005-07-20 | 2007-01-25 | International Business Machines Corporation | Sea-of-fins structure on a semiconductor substrate and method of fabrication |
US8609499B2 (en) * | 2012-01-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and the methods for forming the same |
US20140103451A1 (en) * | 2012-10-17 | 2014-04-17 | International Business Machines Corporation | Finfet circuits with various fin heights |
US9012287B2 (en) * | 2012-11-14 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell layout for SRAM FinFET transistors |
US8987790B2 (en) * | 2012-11-26 | 2015-03-24 | International Business Machines Corporation | Fin isolation in multi-gate field effect transistors |
TWI588596B (zh) * | 2013-08-15 | 2017-06-21 | 聯華電子股份有限公司 | 產生佈局圖案的方法 |
US9276115B2 (en) * | 2013-08-29 | 2016-03-01 | Globalfoundries Inc. | Semiconductor devices and methods of manufacture |
KR102083492B1 (ko) * | 2013-09-26 | 2020-03-02 | 삼성전자 주식회사 | FinFET 소자를 위한 더미 셀 어레이 및 이를 포함한 반도체 집적 회로 |
US9236480B2 (en) * | 2013-10-02 | 2016-01-12 | Globalfoundries Inc. | Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices |
US9373720B2 (en) * | 2013-10-14 | 2016-06-21 | Globalfoundries Inc. | Three-dimensional transistor with improved channel mobility |
US9991285B2 (en) * | 2013-10-30 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming FinFET device |
US20150171217A1 (en) * | 2013-12-12 | 2015-06-18 | Texas Instruments Incorporated | Design and integration of finfet device |
KR102208063B1 (ko) * | 2014-04-22 | 2021-01-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9490129B2 (en) * | 2014-05-08 | 2016-11-08 | GlobalFoundries, Inc. | Integrated circuits having improved gate structures and methods for fabricating same |
US9331074B1 (en) * | 2015-01-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN104716046A (zh) * | 2015-03-16 | 2015-06-17 | 上海华力微电子有限公司 | 一种用于制备鳍式场效应晶体管的方法 |
US9537007B2 (en) * | 2015-04-07 | 2017-01-03 | Qualcomm Incorporated | FinFET with cut gate stressor |
US10269968B2 (en) * | 2015-06-03 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
-
2016
- 2016-07-28 WO PCT/US2016/044474 patent/WO2017027224A1/en active Application Filing
- 2016-07-28 US US15/222,278 patent/US9721793B2/en active Active
- 2016-07-28 CN CN201680051368.8A patent/CN108028268B/zh active Active
- 2016-07-28 KR KR1020187006464A patent/KR102545872B1/ko active IP Right Grant
- 2016-07-28 JP JP2018506291A patent/JP6630896B2/ja active Active
- 2016-08-05 TW TW105124861A patent/TWI594318B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR20180029094A (ko) | 2018-03-19 |
US20170040162A1 (en) | 2017-02-09 |
TW201715602A (zh) | 2017-05-01 |
US9721793B2 (en) | 2017-08-01 |
TWI594318B (zh) | 2017-08-01 |
WO2017027224A1 (en) | 2017-02-16 |
KR102545872B1 (ko) | 2023-06-20 |
CN108028268B (zh) | 2021-01-01 |
JP6630896B2 (ja) | 2020-01-15 |
CN108028268A (zh) | 2018-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6630896B2 (ja) | ダミーゲートを用いないパターニング方法 | |
CN108780777B (zh) | 利用选择性沉积对金属和通孔进行自对准 | |
TWI605561B (zh) | 具有蝕刻停止層於傳導線上方的互連結構 | |
US20170148637A1 (en) | Methods of Forming Etch Masks for Sub-Resolution Substrate Patterning | |
CN109545684B (zh) | 半导体结构及其形成方法 | |
TWI633583B (zh) | 形成記憶體fin圖案的方法與系統 | |
JP2002217170A (ja) | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 | |
TW201709464A (zh) | 利用使用由下而上的交聯之介電質的影像調性反轉以用於後段製程(beol)互連 | |
TWI628746B (zh) | 半導體結構及其製造方法 | |
US10410913B2 (en) | Multi-layer metal contacts | |
JP6903114B2 (ja) | 半導体装置の製造方法 | |
US20170256628A1 (en) | Methods of forming fine patterns | |
SG182041A1 (en) | Semiconductor devices having through-contacts and related fabrication methods | |
US10366889B2 (en) | Method of forming semiconductor device | |
TW201822332A (zh) | 半導體元件及其製作方法 | |
US11145541B2 (en) | Conductive via and metal line end fabrication and structures resulting therefrom | |
US9824916B2 (en) | Wiring structure and method of forming a wiring structure | |
JP4634180B2 (ja) | 半導体装置及びその製造方法 | |
TWI633625B (zh) | 使用間隔物蝕刻溝槽形成柵欄導體 | |
TWI711120B (zh) | 非平面半導體元件、積體電路、鰭式場效應電晶體陣列 | |
CN104037122B (zh) | 多层金属接触件 | |
JP2006108571A (ja) | 半導体装置 | |
KR100466026B1 (ko) | 고집적 반도체 소자의 도전체 패턴 제조 방법 | |
JP2008103501A (ja) | 半導体装置の製造方法及び半導体装置 | |
US10515818B2 (en) | Semiconductor methods and devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180409 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190528 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190724 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20191001 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20191029 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20191029 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6630896 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |