US20150171217A1 - Design and integration of finfet device - Google Patents

Design and integration of finfet device Download PDF

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US20150171217A1
US20150171217A1 US14/499,957 US201414499957A US2015171217A1 US 20150171217 A1 US20150171217 A1 US 20150171217A1 US 201414499957 A US201414499957 A US 201414499957A US 2015171217 A1 US2015171217 A1 US 2015171217A1
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Prior art keywords
fin
finfet
isolation oxide
height
gate
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US14/499,957
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Ryoung-han Kim
Kwanyong LIM
Youn Sung Choi
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US14/499,957 priority Critical patent/US20150171217A1/en
Priority to CN201480067898.2A priority patent/CN105814672A/en
Priority to EP14869197.5A priority patent/EP3080835A4/en
Priority to PCT/US2014/070116 priority patent/WO2015089454A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, YOUN SUNG, KIM, RYOUNG-HAN, LIM, Kwanyong
Publication of US20150171217A1 publication Critical patent/US20150171217A1/en
Priority to US15/843,629 priority patent/US20180108564A1/en
Priority to US16/414,525 priority patent/US10950488B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L27/11—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials

Definitions

  • This invention relates to the field of integrated circuits. More particularly, this invention relates to fin field effect transistors (finFETs) in integrated circuits.
  • finFETs fin field effect transistors
  • An integrated circuit may include finFETs in logic or memory circuits. FinFETs may desirably provide increased on-state currents compared to planar FETs having similar footprints. FinFETs may be formed with the fins having constant pitch and width, and the gates having constant width and pitch, so as to provide a desired circuit density. It may be desirable to have some instances of the finFETs with higher on-state currents than adjacent finFETs, for example in delay circuits or in drivers of static random access memory (SRAM) cells. Forming finFETs with varying on-state currents in constant width and pitch configurations may involve adding additional fins to the finFETs, undesirably increasing footprints of the finFETs. It may further be problematic to increase the on-state current by a fractional amount, such as 50 percent, by adding a fin, since fins are added in integral numbers.
  • a fractional amount such as 50 percent
  • An integrated circuit containing finFETs may be formed so that fins of the finFETs extend above an isolation oxide formed over a substrate of the integrated circuit.
  • a first finFET and a second finFET have exposed fin heights which are different by at least 25 percent.
  • the exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide.
  • Gates are formed over the fins, extending down the sidewalls of the fins, so that finFETs with greater exposed fin heights have greater effective channel widths and hence greater on-state currents compared with similar finFETs with lesser exposed fin heights.
  • a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform.
  • the fin height is the height of a top of the fin above the substrate adjacent to the fin, and so includes a portion of the fin adjacent to the isolation oxide.
  • the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.
  • FIG. 1 is a cross section of an example integrated circuit containing finFETs.
  • FIG. 2A through FIG. 2H are cross sections of the integrated circuit of FIG. 1 , depicted in successive stages of fabrication.
  • FIG. 3A and FIG. 3B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 1 and FIG. 2A through FIG. 2H .
  • FIG. 4 is a cross section of another example integrated circuit containing finFETs.
  • FIG. 5A through FIG. 5D are cross sections of the integrated circuit of FIG. 4 , depicted in successive stages of fabrication.
  • FIG. 6A and FIG. 6B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 4 and FIG. 5A through FIG. 5D .
  • An integrated circuit containing finFETs may be formed so that fins of the finFETs extend above an isolation oxide formed over a substrate of the integrated circuit.
  • a first finFET has a first exposed fin height and a second finFET has a second exposed fin height; the first exposed fin height and the second exposed fin height are different by at least 25 percent.
  • the exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide.
  • Gates are formed over the fins, extending down the sidewalls of the fins, so that finFETs with greater exposed fin heights have greater effective channel widths and hence greater on-state currents compared with similar finFETs with lesser exposed fin heights.
  • Fin widths of the first finFET and the second finFET may be substantially equal. Gate widths of the first finFET and the second finFET may be substantially equal.
  • the first finFET and the second finFET may be part of a plurality of finFETs with substantially uniform fin width and pitch, and/or substantially uniform gate width and pitch.
  • the first finFET and the second finFET may be part of an SRAM cell.
  • a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform.
  • the fin height is the height of a top of the fin above the substrate adjacent to the fin, including a portion of the fin adjacent to the isolation oxide.
  • the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.
  • FIG. 1 is a cross section of an example integrated circuit containing finFETs.
  • the integrated circuit 100 is formed on a substrate 102 which includes semiconductor material such as silicon.
  • Fins 104 are formed on the substrate 102 , for example by forming an etch mask covering areas for the fins 104 and removing semiconductor material from the substrate 102 between the fins 104 .
  • Widths 106 of the fins 104 may be substantially equal.
  • Pitch distances 108 between centers of adjacent fins 104 may be substantially equal.
  • Isolation oxide 110 is disposed over the substrate 102 adjacent to the fins 104 .
  • the isolation oxide 110 may possibly include silicon nitride or other dielectric material.
  • Gates 112 are disposed across the fins 104 and extend substantially down to the isolation oxide 110 .
  • the gates 112 may be metal replacement gates as depicted in FIG. 1 or may be polysilicon gates.
  • the integrated circuit 100 includes at least one instance of a first finFET 114 and at least one instance of a second finFET 116 . Instances of the first finFET 114 have an exposed fin height 118 which is at least 25 percent less than an exposed fin height 120 of instances of the second finFET 116 . A thickness 122 of the isolation oxide 110 is substantially equal in instances of the first finFET 114 and instances of the second finFET 116 . Fin heights 124 of the first finFETs 114 are less than fin heights 126 of the second finFETs 116 .
  • instances of the first finFETs 114 may include exactly one instance of the gates 112 over exactly one instance of the fins 104 , may include exactly one instance of the gates 112 over a plurality of instances of the fins 104 , may include a plurality of instances of the gates 112 over exactly one instance of the fins 104 , and/or may include a plurality of instances of the gates 112 over a plurality of instances of the fins 104 .
  • instances of the second finFETs 116 may include one or more instances of the gates 112 over one or more instances of the fins 104 .
  • On-state current in the finFETs 114 and 116 is an increasing function of the exposed fin heights 118 and 120 and fin widths, and a decreasing function of widths of the gates 112 .
  • Instances of the first finFET 114 have a lower on-state current than comparable instances of the second finFET 116 with equal numbers of gates 112 over equal numbers of fins 104 .
  • the exposed fin height 118 of the first finFETs 114 may be selected to provide a desired on-state current. Forming the integrated circuit 100 with instances of the first finFET 114 and the second finFET 116 may advantageously provide desired circuit densities compared to an integrated circuit with substantially equal exposed fin heights in all finFETs.
  • FIG. 2A through FIG. 2H are cross sections of the integrated circuit of FIG. 1 , depicted in successive stages of fabrication.
  • the integrated circuit 100 is formed on the substrate 102 , which may be, for example, a single crystal silicon wafer or a silicon-on-insulator (SOI) wafer.
  • the substrate 102 includes semiconductor material such as crystalline silicon or a silicon-containing compound semiconductor.
  • the fins 104 are formed on the semiconductor material of the substrate 102 .
  • the fins 104 may be formed, for example, by forming an etch mask over the substrate 102 which covers areas for the fins 104 and subsequently removing the semiconductor material exposed by the etch mask, leaving the fins 104 .
  • the etch mask is removed after the fins 104 are formed.
  • the fins 104 may be formed by an epitaxial growth process on the substrate 102 . Heights of the fins 104 at this stage of fabrication are substantially equal. Widths 106 of the fins 104 may be substantially equal. Pitch distances 108 between centers of adjacent fins 104 may be substantially equal. Forming the fins 104 with substantially equal widths 106 and/or substantially equal pitch distances 108 may advantageously reduce a size and a fabrication cost of the integrated circuit 100 .
  • the isolation oxide 110 is formed over the substrate 102 between the fins 104 .
  • the isolation oxide 110 may be formed as part of a field oxide formation process, such as a shallow trench isolation (STI) process. Exposed fin heights of the fins 104 at this stage of fabrication are substantially equal.
  • STI shallow trench isolation
  • the anti-reflection coating 128 may include a lower layer of spin-on organic resin, a middle layer of organic polymer material such as an organosilicate copolymer in a 1-methoxy-2-acetoxypropane (PGMEA) solvent, and a top layer of inorganic material such as amorphous carbon.
  • PGMEA 1-methoxy-2-acetoxypropane
  • An etch mask 130 is formed over the layer of anti-reflection coating 128 so as to expose areas for instances of the first finFET 114 and cover areas for instances of the second finFET 116 .
  • the etch mask 130 may include photoresist formed by a photolithographic process.
  • the layer of anti-reflection coating 128 is removed in areas exposed by the etch mask 130 so as to expose the fins 104 in areas for instances of the first finFET 114 and cover the fins 104 in areas for the second finFET 116 .
  • the layer of anti-reflection coating 128 may be removed by a reactive ion etch (RIE) process using oxygen and fluorine radicals.
  • RIE reactive ion etch
  • semiconductor material is removed from tops of the fins 104 exposed by the layer of anti-reflection coating 128 .
  • the semiconductor material may be removed by an RIE process using fluorine and/or bromine radicals.
  • the semiconductor material may be removed in a timed-etch mode, so that a desired exposed fin height is obtained for the fins 104 exposed by the layer of anti-reflection coating 128 .
  • the semiconductor material is removed using an etch process that is selective to the isolation oxide 110 , so that a thickness of the isolation oxide 110 removed is significantly less than the thickness of semiconductor removed from the fins 104 .
  • the layer of anti-reflection coating 128 of FIG. 2D is removed, for example by an ashing process.
  • the exposed fin height 118 in the first finFET 114 and the exposed fin height 120 in the second finFET 116 are at desired values.
  • Gate dielectric layers are formed on the fins 104 , possibly by thermally oxidizing a layer of the semiconductor material in the fins 104 .
  • the layer of anti-reflection coating 128 of FIG. 2B through FIG. 2D may be dispensed with, and the etch mask 130 of FIG. 2B formed directly over the fins 104 .
  • polysilicon gates 132 are formed over the fins 104 so as to extend substantially down to the isolation oxide 110 .
  • the polysilicon gates 132 may be formed to have uniform widths 134 and/or uniform pitch distances 136 . Forming the polysilicon gates 132 with substantially equal widths 134 and/or substantially equal pitch distances 136 may advantageously reduce a size and a fabrication cost of the integrated circuit 100 .
  • the integrated circuit 100 may be completed with the polysilicon gates 132 in place, or the fabrication sequence may optionally continue with a metal replacement gate process described in reference to FIG. 2G and FIG. 2H . Completing the integrated circuit 100 with the polysilicon gates 132 in place may advantageously provide a desired low fabrication cost.
  • a dielectric layer 138 is formed over the polysilicon gates 132 and planarized so as to expose top surfaces of the polysilicon gates 132 .
  • the dielectric layer 138 may include, for example, silicon dioxide formed from methylsilsesquioxane (MSQ), or may include silicon dioxide formed by a plasma enhanced chemical vapor deposition (PECVD) process using ozone, known as a high aspect ratio process (HARP).
  • PECVD plasma enhanced chemical vapor deposition
  • the dielectric layer 138 may be planarized using a chemical mechanical polish (CMP) process or a resist etchback (REB) process.
  • CMP chemical mechanical polish
  • REB resist etchback
  • the polysilicon gates 132 of FIG. 2G are removed, leaving gate cavities 140 in the dielectric layer 138 .
  • the polysilicon gates 132 may be removed, for example, using an aqueous solution of ammonium hydroxide or tetra-methyl ammonium hydroxide.
  • the gate dielectric layers may also be removed.
  • Replacement metal gates are formed in the gate cavities 140 to form the structure of FIG. 1 . Forming metal replacement gates may advantageously provide a desired level of on-state current in the finFETs 114 and 116 .
  • FIG. 3A and FIG. 3B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 1 and FIG. 2A through FIG. 2H .
  • the integrated circuit 300 is formed on a substrate 302 as described in reference to FIG. 2A .
  • Fins 304 and isolation oxide 310 are formed on the substrate 302 , for example as described in reference to FIG. 2A .
  • the SRAM contains a plurality of SRAM cells 342 ; each SRAM cell 342 includes two driver finFETs 344 , two load finFETs 346 and two passgate finFETs 348 .
  • the isolation oxide 310 is substantially uniformly thick in the SRAM cells 342 , as described in reference to FIG.
  • Reliable read and write operations in the SRAM cells 342 require the driver finFETs 344 to have on-state currents which are, for example, 25 percent to 100 percent higher than on-state currents in the passgate finFETs 348 .
  • the passgate finFETs 348 have fin heights which are less than fin heights of the driver finFETs 344 , so that the passgate finFETs 348 have exposed fin heights which are at least 25 percent lower than exposed fin heights of the driver finFETs 344 , which advantageously allows forming the driver finFETs 344 with a single fin 304 for each driver finFET 344 . This provides a smaller SRAM area compared to an SRAM in which two fins are required for the driver finFETs to attain the necessary on-state current.
  • gates 312 are formed over the fins 304 .
  • the driver finFETs 344 , load finFETs 346 and passgate finFETs 348 have one gate 312 each.
  • the gates 312 may be polysilicon gates or may be metal replacement gates.
  • the gates 312 may be formed with uniform width and uniform pitch distances, thereby advantageously providing a reduced area for the SRAM compared with variable gate widths and/or pitch distances to attain the necessary on-state currents in the driver finFETs and passgate finFETs.
  • FIG. 4 is a cross section of another example integrated circuit containing finFETs.
  • the integrated circuit 400 is formed on a substrate 402 which includes semiconductor material such as silicon.
  • Fins 404 are formed on the substrate 402 , for example by forming an etch mask covering areas for the fins 404 and removing semiconductor material from the substrate 402 between the fins 404 .
  • Widths 406 of the fins 404 may be substantially equal.
  • Pitch distances 408 between centers of adjacent fins 404 may be substantially equal.
  • Fin heights 424 of the first finFETs 414 are substantially equal to fin heights 426 of the second finFETs 416 .
  • Isolation oxide 410 is disposed over the substrate 402 adjacent to the fins 404 .
  • the isolation oxide 410 may possibly include silicon nitride or other dielectric material.
  • the integrated circuit 400 includes at least one instance of a first finFET 414 and at least one instance of a second finFET 416 . Instances of the first finFET 414 have a thickness 422 of the isolation oxide 410 which less than a thickness 450 of the isolation oxide 410 in instances of the second finFET 416 , so that instances of the first finFET 414 have an exposed fin height 418 which is at least 25 percent more than an exposed fin height 420 of instances of the second finFET 416 .
  • Gates 412 are disposed across the fins 404 and extend substantially down to the isolation oxide 410 .
  • the gates 412 may be metal replacement gates as depicted in FIG. 4 or may be polysilicon gates.
  • Instances of the first finFET 414 and instances of the second finFET 416 may include one or more instances of the gates 412 over one or more instances of the fins 404 .
  • first finFET 414 has a higher on-state current than comparable instances of the second finFET 416 with equal numbers of gates 412 over equal numbers of fins 404 .
  • the thickness 450 of the isolation oxide 410 in the first finFETs 414 may be selected to provide a desired exposed fin height 418 and thus a desired on-state current. Forming the integrated circuit 400 with instances of the first finFET 414 and the second finFET 416 may advantageously provide desired circuit densities compared to an integrated circuit with substantially equal exposed fin heights in all finFETs.
  • FIG. 5A through FIG. 5D are cross sections of the integrated circuit of FIG. 4 , depicted in successive stages of fabrication.
  • the integrated circuit 400 is formed on the substrate 402 , which may be a single crystal silicon wafer or an SOI wafer.
  • the substrate 402 includes semiconductor material such as crystalline silicon or a silicon-containing compound semiconductor.
  • the fins 404 are formed in the semiconductor material of the substrate 402 .
  • the fins 404 may be formed, for example, by forming an etch mask over the substrate 402 which covers areas for the fins 404 and subsequently removing the semiconductor material exposed by the etch mask, leaving the fins 404 .
  • the etch mask is removed after the fins 404 are formed. Heights of the fins 404 are substantially equal. Widths 406 of the fins 404 may be substantially equal. Pitch distances 408 between centers of adjacent fins 404 may be substantially equal. Forming the fins 404 with substantially equal widths 406 and/or substantially equal pitch distances 408 may advantageously reduce a size and a fabrication cost of the integrated circuit 400 .
  • the isolation oxide 410 is formed over the substrate 402 between the fins 404 .
  • the isolation oxide 410 may be formed as part of a field oxide formation process, such as an STI process.
  • the isolation oxide 410 is substantially uniform in thickness at this stage of fabrication, so that exposed fin heights of the fins 404 at this stage of fabrication are substantially equal.
  • An etch mask 430 is formed over the fins 404 and the isolation oxide 410 so as to expose areas for instances of the first finFET 414 and cover areas for instances of the second finFET 416 .
  • the etch mask 430 may include photoresist formed by a photolithographic process, may include anti-reflection material, and/or may include hard mask material such as amorphous carbon.
  • a portion of the isolation oxide 410 is removed in areas exposed by the etch mask 430 .
  • the isolation oxide 410 may be removed using an RIE process.
  • the isolation oxide 410 is removed using an etch process which is selective to the semiconductor material in the fins 404 , so that a thickness of semiconductor removed from the fins 404 is significantly less than the thickness of the isolation oxide 410 removed.
  • the etch mask 430 of FIG. 5B is removed, for example by an ashing process.
  • the exposed fin height 418 in the first finFET 414 and the exposed fin height 420 in the second finFET 416 are at desired values. Instances of the first finFET 414 have an exposed fin height 418 which is at least 25 percent more than an exposed fin height 420 of instances of the second finFET 416 .
  • Gate dielectric layers are formed on the fins 404 , possibly by thermally oxidizing a layer of the semiconductor material in the fins 404 .
  • polysilicon gates 432 are formed over the fins 404 so as to extend substantially down to the isolation oxide 410 .
  • the polysilicon gates 432 may be formed to have uniform widths 434 and/or uniform pitch distances 436 . Forming the polysilicon gates 432 with substantially equal widths 434 and/or substantially equal pitch distances 436 may advantageously reduce a size and a fabrication cost of the integrated circuit 400 .
  • the integrated circuit 400 may be completed with the polysilicon gates 432 in place, or metal replacement gates may be formed as described in reference to FIG. 2G and FIG. 2H , so as to form the structure of FIG. 4 . Completing the integrated circuit 400 with the polysilicon gates 432 in place may advantageously provide a desired low fabrication cost. Forming metal replacement gates may advantageously provide a desired level of on-state current in the finFETs 414 and 416 .
  • FIG. 6A and FIG. 6B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 4 and FIG. 5A through FIG. 5D .
  • the integrated circuit 600 is formed on a substrate 602 as described in reference to FIG. 2A .
  • Fins 604 and isolation oxide 610 are formed on the substrate 602 , for example as described in reference to FIG. 5A .
  • the SRAM contains a plurality of SRAM cells 642 ; each SRAM cell 642 includes two driver finFETs 644 , two load finFETs 646 and two passgate finFETs 648 .
  • Fin heights of the driver finFETs 644 , load finFETs 646 and passgate finFETs 648 are substantially equal, as described in reference to FIG. 5A through FIG. 5D .
  • Reliable read and write operations in the SRAM cells 642 require the driver finFETs 644 to have on-state currents which are, for example, 25 percent to 100 percent higher than on-state currents in the passgate finFETs 648 .
  • the isolation oxide 610 is thinner in the driver finFETs 644 than in the passgate finFETs 648 so that the passgate finFETs 648 have exposed fin heights which are at least 25 percent lower than exposed fin heights of the driver finFETs 644 , which advantageously allows forming the driver finFETs 644 with a single fin 604 for each driver finFET 644 .
  • This provides a smaller SRAM area compared to an SRAM in which two fins are required for the driver finFETs to attain the necessary on-state current.
  • gates 612 are formed over the fins 604 .
  • the driver finFETs 644 , load finFETs 646 and passgate finFETs 648 have one gate 612 each.
  • the gates 612 may be polysilicon gates or may be metal replacement gates.
  • the gates 612 may be formed with uniform width and uniform pitch distances, thereby advantageously providing a reduced area for the SRAM compared with variable gate widths and/or pitch distances to attain the necessary on-state currents in the driver finFETs and passgate finFETs.

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Abstract

An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of priority under U.S.C. §119(e) of U.S. Provisional Application 61/915,038 (Texas Instruments docket number TI-72131P), filed Dec. 12, 2013, which is hereby incorporated by reference in its entirety.
    • FIELD OF THE INVENTION
  • This invention relates to the field of integrated circuits. More particularly, this invention relates to fin field effect transistors (finFETs) in integrated circuits.
    • BACKGROUND OF THE INVENTION
  • An integrated circuit may include finFETs in logic or memory circuits. FinFETs may desirably provide increased on-state currents compared to planar FETs having similar footprints. FinFETs may be formed with the fins having constant pitch and width, and the gates having constant width and pitch, so as to provide a desired circuit density. It may be desirable to have some instances of the finFETs with higher on-state currents than adjacent finFETs, for example in delay circuits or in drivers of static random access memory (SRAM) cells. Forming finFETs with varying on-state currents in constant width and pitch configurations may involve adding additional fins to the finFETs, undesirably increasing footprints of the finFETs. It may further be problematic to increase the on-state current by a fractional amount, such as 50 percent, by adding a fin, since fins are added in integral numbers.
    • SUMMARY OF THE INVENTION
  • The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
  • An integrated circuit containing finFETs may be formed so that fins of the finFETs extend above an isolation oxide formed over a substrate of the integrated circuit. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins, extending down the sidewalls of the fins, so that finFETs with greater exposed fin heights have greater effective channel widths and hence greater on-state currents compared with similar finFETs with lesser exposed fin heights.
  • In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate adjacent to the fin, and so includes a portion of the fin adjacent to the isolation oxide. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.
    • DESCRIPTION OF THE VIEWS OF THE DRAWING
  • FIG. 1 is a cross section of an example integrated circuit containing finFETs.
  • FIG. 2A through FIG. 2H are cross sections of the integrated circuit of FIG. 1, depicted in successive stages of fabrication.
  • FIG. 3A and FIG. 3B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 1 and FIG. 2A through FIG. 2H.
  • FIG. 4 is a cross section of another example integrated circuit containing finFETs.
  • FIG. 5A through FIG. 5D are cross sections of the integrated circuit of FIG. 4, depicted in successive stages of fabrication.
  • FIG. 6A and FIG. 6B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 4 and FIG. 5A through FIG. 5D.
    •  DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • The following application contains related material and is hereby incorporated in its entirety: Application xx/xxx,xxx entitled “METHOD OF PRINTING MULTIPLE STRUCTURE WIDTHS USING SPACER DOUBLE PATTERNING” (Attorney docket number TI-72133) filed concurrently with this application.
  • An integrated circuit containing finFETs may be formed so that fins of the finFETs extend above an isolation oxide formed over a substrate of the integrated circuit. A first finFET has a first exposed fin height and a second finFET has a second exposed fin height; the first exposed fin height and the second exposed fin height are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins, extending down the sidewalls of the fins, so that finFETs with greater exposed fin heights have greater effective channel widths and hence greater on-state currents compared with similar finFETs with lesser exposed fin heights.
  • Fin widths of the first finFET and the second finFET may be substantially equal. Gate widths of the first finFET and the second finFET may be substantially equal. The first finFET and the second finFET may be part of a plurality of finFETs with substantially uniform fin width and pitch, and/or substantially uniform gate width and pitch. The first finFET and the second finFET may be part of an SRAM cell.
  • In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate adjacent to the fin, including a portion of the fin adjacent to the isolation oxide. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.
  • FIG. 1 is a cross section of an example integrated circuit containing finFETs. The integrated circuit 100 is formed on a substrate 102 which includes semiconductor material such as silicon. Fins 104 are formed on the substrate 102, for example by forming an etch mask covering areas for the fins 104 and removing semiconductor material from the substrate 102 between the fins 104. Widths 106 of the fins 104 may be substantially equal. Pitch distances 108 between centers of adjacent fins 104 may be substantially equal.
  • Isolation oxide 110 is disposed over the substrate 102 adjacent to the fins 104. The isolation oxide 110 may possibly include silicon nitride or other dielectric material. Gates 112 are disposed across the fins 104 and extend substantially down to the isolation oxide 110. The gates 112 may be metal replacement gates as depicted in FIG. 1 or may be polysilicon gates.
  • The integrated circuit 100 includes at least one instance of a first finFET 114 and at least one instance of a second finFET 116. Instances of the first finFET 114 have an exposed fin height 118 which is at least 25 percent less than an exposed fin height 120 of instances of the second finFET 116. A thickness 122 of the isolation oxide 110 is substantially equal in instances of the first finFET 114 and instances of the second finFET 116. Fin heights 124 of the first finFETs 114 are less than fin heights 126 of the second finFETs 116. It will be recognized that instances of the first finFETs 114 may include exactly one instance of the gates 112 over exactly one instance of the fins 104, may include exactly one instance of the gates 112 over a plurality of instances of the fins 104, may include a plurality of instances of the gates 112 over exactly one instance of the fins 104, and/or may include a plurality of instances of the gates 112 over a plurality of instances of the fins 104. Similarly, instances of the second finFETs 116 may include one or more instances of the gates 112 over one or more instances of the fins 104.
  • On-state current in the finFETs 114 and 116 is an increasing function of the exposed fin heights 118 and 120 and fin widths, and a decreasing function of widths of the gates 112. Instances of the first finFET 114 have a lower on-state current than comparable instances of the second finFET 116 with equal numbers of gates 112 over equal numbers of fins 104. The exposed fin height 118 of the first finFETs 114 may be selected to provide a desired on-state current. Forming the integrated circuit 100 with instances of the first finFET 114 and the second finFET 116 may advantageously provide desired circuit densities compared to an integrated circuit with substantially equal exposed fin heights in all finFETs.
  • FIG. 2A through FIG. 2H are cross sections of the integrated circuit of FIG. 1, depicted in successive stages of fabrication. Referring to FIG. 2A, the integrated circuit 100 is formed on the substrate 102, which may be, for example, a single crystal silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate 102 includes semiconductor material such as crystalline silicon or a silicon-containing compound semiconductor.
  • The fins 104 are formed on the semiconductor material of the substrate 102. The fins 104 may be formed, for example, by forming an etch mask over the substrate 102 which covers areas for the fins 104 and subsequently removing the semiconductor material exposed by the etch mask, leaving the fins 104. The etch mask is removed after the fins 104 are formed. Alternatively, the fins 104 may be formed by an epitaxial growth process on the substrate 102. Heights of the fins 104 at this stage of fabrication are substantially equal. Widths 106 of the fins 104 may be substantially equal. Pitch distances 108 between centers of adjacent fins 104 may be substantially equal. Forming the fins 104 with substantially equal widths 106 and/or substantially equal pitch distances 108 may advantageously reduce a size and a fabrication cost of the integrated circuit 100.
  • The isolation oxide 110 is formed over the substrate 102 between the fins 104. The isolation oxide 110 may be formed as part of a field oxide formation process, such as a shallow trench isolation (STI) process. Exposed fin heights of the fins 104 at this stage of fabrication are substantially equal.
  • Referring to FIG. 2B, a layer of anti-reflection coating 128 is formed over the fins 104 and the isolation oxide 110. The anti-reflection coating 128 may include a lower layer of spin-on organic resin, a middle layer of organic polymer material such as an organosilicate copolymer in a 1-methoxy-2-acetoxypropane (PGMEA) solvent, and a top layer of inorganic material such as amorphous carbon.
  • An etch mask 130 is formed over the layer of anti-reflection coating 128 so as to expose areas for instances of the first finFET 114 and cover areas for instances of the second finFET 116. The etch mask 130 may include photoresist formed by a photolithographic process.
  • Referring to FIG. 2C, the layer of anti-reflection coating 128 is removed in areas exposed by the etch mask 130 so as to expose the fins 104 in areas for instances of the first finFET 114 and cover the fins 104 in areas for the second finFET 116. The layer of anti-reflection coating 128 may be removed by a reactive ion etch (RIE) process using oxygen and fluorine radicals. The etch mask 130 is subsequently removed.
  • Referring to FIG. 2D, semiconductor material is removed from tops of the fins 104 exposed by the layer of anti-reflection coating 128. The semiconductor material may be removed by an RIE process using fluorine and/or bromine radicals. The semiconductor material may be removed in a timed-etch mode, so that a desired exposed fin height is obtained for the fins 104 exposed by the layer of anti-reflection coating 128. The semiconductor material is removed using an etch process that is selective to the isolation oxide 110, so that a thickness of the isolation oxide 110 removed is significantly less than the thickness of semiconductor removed from the fins 104.
  • Referring to FIG. 2E, the layer of anti-reflection coating 128 of FIG. 2D is removed, for example by an ashing process. After the layer of anti-reflection coating 128 is removed, the exposed fin height 118 in the first finFET 114 and the exposed fin height 120 in the second finFET 116 are at desired values. Gate dielectric layers are formed on the fins 104, possibly by thermally oxidizing a layer of the semiconductor material in the fins 104.
  • Alternatively, the layer of anti-reflection coating 128 of FIG. 2B through FIG. 2D may be dispensed with, and the etch mask 130 of FIG. 2B formed directly over the fins 104.
  • Referring to FIG. 2F, polysilicon gates 132 are formed over the fins 104 so as to extend substantially down to the isolation oxide 110. The polysilicon gates 132 may be formed to have uniform widths 134 and/or uniform pitch distances 136. Forming the polysilicon gates 132 with substantially equal widths 134 and/or substantially equal pitch distances 136 may advantageously reduce a size and a fabrication cost of the integrated circuit 100. The integrated circuit 100 may be completed with the polysilicon gates 132 in place, or the fabrication sequence may optionally continue with a metal replacement gate process described in reference to FIG. 2G and FIG. 2H. Completing the integrated circuit 100 with the polysilicon gates 132 in place may advantageously provide a desired low fabrication cost.
  • Referring to FIG. 2G, a dielectric layer 138 is formed over the polysilicon gates 132 and planarized so as to expose top surfaces of the polysilicon gates 132. The dielectric layer 138 may include, for example, silicon dioxide formed from methylsilsesquioxane (MSQ), or may include silicon dioxide formed by a plasma enhanced chemical vapor deposition (PECVD) process using ozone, known as a high aspect ratio process (HARP). The dielectric layer 138 may be planarized using a chemical mechanical polish (CMP) process or a resist etchback (REB) process.
  • Referring to FIG. 2H, the polysilicon gates 132 of FIG. 2G are removed, leaving gate cavities 140 in the dielectric layer 138. The polysilicon gates 132 may be removed, for example, using an aqueous solution of ammonium hydroxide or tetra-methyl ammonium hydroxide. The gate dielectric layers may also be removed. Replacement metal gates are formed in the gate cavities 140 to form the structure of FIG. 1. Forming metal replacement gates may advantageously provide a desired level of on-state current in the finFETs 114 and 116.
  • FIG. 3A and FIG. 3B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 1 and FIG. 2A through FIG. 2H. Referring to FIG. 3A, the integrated circuit 300 is formed on a substrate 302 as described in reference to FIG. 2A. Fins 304 and isolation oxide 310 are formed on the substrate 302, for example as described in reference to FIG. 2A. The SRAM contains a plurality of SRAM cells 342; each SRAM cell 342 includes two driver finFETs 344, two load finFETs 346 and two passgate finFETs 348. The isolation oxide 310 is substantially uniformly thick in the SRAM cells 342, as described in reference to FIG. 2A through FIG. 2H. Reliable read and write operations in the SRAM cells 342 require the driver finFETs 344 to have on-state currents which are, for example, 25 percent to 100 percent higher than on-state currents in the passgate finFETs 348. The passgate finFETs 348 have fin heights which are less than fin heights of the driver finFETs 344, so that the passgate finFETs 348 have exposed fin heights which are at least 25 percent lower than exposed fin heights of the driver finFETs 344, which advantageously allows forming the driver finFETs 344 with a single fin 304 for each driver finFET 344. This provides a smaller SRAM area compared to an SRAM in which two fins are required for the driver finFETs to attain the necessary on-state current.
  • Referring to FIG. 3B, gates 312 are formed over the fins 304. The driver finFETs 344, load finFETs 346 and passgate finFETs 348 have one gate 312 each. The gates 312 may be polysilicon gates or may be metal replacement gates. The gates 312 may be formed with uniform width and uniform pitch distances, thereby advantageously providing a reduced area for the SRAM compared with variable gate widths and/or pitch distances to attain the necessary on-state currents in the driver finFETs and passgate finFETs.
  • FIG. 4 is a cross section of another example integrated circuit containing finFETs. The integrated circuit 400 is formed on a substrate 402 which includes semiconductor material such as silicon. Fins 404 are formed on the substrate 402, for example by forming an etch mask covering areas for the fins 404 and removing semiconductor material from the substrate 402 between the fins 404. Widths 406 of the fins 404 may be substantially equal. Pitch distances 408 between centers of adjacent fins 404 may be substantially equal. Fin heights 424 of the first finFETs 414 are substantially equal to fin heights 426 of the second finFETs 416.
  • Isolation oxide 410 is disposed over the substrate 402 adjacent to the fins 404. The isolation oxide 410 may possibly include silicon nitride or other dielectric material. The integrated circuit 400 includes at least one instance of a first finFET 414 and at least one instance of a second finFET 416. Instances of the first finFET 414 have a thickness 422 of the isolation oxide 410 which less than a thickness 450 of the isolation oxide 410 in instances of the second finFET 416, so that instances of the first finFET 414 have an exposed fin height 418 which is at least 25 percent more than an exposed fin height 420 of instances of the second finFET 416.
  • Gates 412 are disposed across the fins 404 and extend substantially down to the isolation oxide 410. The gates 412 may be metal replacement gates as depicted in FIG. 4 or may be polysilicon gates. Instances of the first finFET 414 and instances of the second finFET 416 may include one or more instances of the gates 412 over one or more instances of the fins 404.
  • Instances of the first finFET 414 have a higher on-state current than comparable instances of the second finFET 416 with equal numbers of gates 412 over equal numbers of fins 404. The thickness 450 of the isolation oxide 410 in the first finFETs 414 may be selected to provide a desired exposed fin height 418 and thus a desired on-state current. Forming the integrated circuit 400 with instances of the first finFET 414 and the second finFET 416 may advantageously provide desired circuit densities compared to an integrated circuit with substantially equal exposed fin heights in all finFETs.
  • FIG. 5A through FIG. 5D are cross sections of the integrated circuit of FIG. 4, depicted in successive stages of fabrication. Referring to FIG. 5A, the integrated circuit 400 is formed on the substrate 402, which may be a single crystal silicon wafer or an SOI wafer. The substrate 402 includes semiconductor material such as crystalline silicon or a silicon-containing compound semiconductor.
  • The fins 404 are formed in the semiconductor material of the substrate 402. The fins 404 may be formed, for example, by forming an etch mask over the substrate 402 which covers areas for the fins 404 and subsequently removing the semiconductor material exposed by the etch mask, leaving the fins 404. The etch mask is removed after the fins 404 are formed. Heights of the fins 404 are substantially equal. Widths 406 of the fins 404 may be substantially equal. Pitch distances 408 between centers of adjacent fins 404 may be substantially equal. Forming the fins 404 with substantially equal widths 406 and/or substantially equal pitch distances 408 may advantageously reduce a size and a fabrication cost of the integrated circuit 400.
  • The isolation oxide 410 is formed over the substrate 402 between the fins 404. The isolation oxide 410 may be formed as part of a field oxide formation process, such as an STI process. The isolation oxide 410 is substantially uniform in thickness at this stage of fabrication, so that exposed fin heights of the fins 404 at this stage of fabrication are substantially equal.
  • An etch mask 430 is formed over the fins 404 and the isolation oxide 410 so as to expose areas for instances of the first finFET 414 and cover areas for instances of the second finFET 416. The etch mask 430 may include photoresist formed by a photolithographic process, may include anti-reflection material, and/or may include hard mask material such as amorphous carbon.
  • Referring to FIG. 5B, a portion of the isolation oxide 410 is removed in areas exposed by the etch mask 430. The isolation oxide 410 may be removed using an RIE process. The isolation oxide 410 is removed using an etch process which is selective to the semiconductor material in the fins 404, so that a thickness of semiconductor removed from the fins 404 is significantly less than the thickness of the isolation oxide 410 removed.
  • Referring to FIG. 5C, the etch mask 430 of FIG. 5B is removed, for example by an ashing process. After the etch mask 430 is removed, the exposed fin height 418 in the first finFET 414 and the exposed fin height 420 in the second finFET 416 are at desired values. Instances of the first finFET 414 have an exposed fin height 418 which is at least 25 percent more than an exposed fin height 420 of instances of the second finFET 416. Gate dielectric layers are formed on the fins 404, possibly by thermally oxidizing a layer of the semiconductor material in the fins 404.
  • Referring to FIG. 5D, polysilicon gates 432 are formed over the fins 404 so as to extend substantially down to the isolation oxide 410. The polysilicon gates 432 may be formed to have uniform widths 434 and/or uniform pitch distances 436. Forming the polysilicon gates 432 with substantially equal widths 434 and/or substantially equal pitch distances 436 may advantageously reduce a size and a fabrication cost of the integrated circuit 400. The integrated circuit 400 may be completed with the polysilicon gates 432 in place, or metal replacement gates may be formed as described in reference to FIG. 2G and FIG. 2H, so as to form the structure of FIG. 4. Completing the integrated circuit 400 with the polysilicon gates 432 in place may advantageously provide a desired low fabrication cost. Forming metal replacement gates may advantageously provide a desired level of on-state current in the finFETs 414 and 416.
  • FIG. 6A and FIG. 6B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 4 and FIG. 5A through FIG. 5D. Referring to FIG. 6A, the integrated circuit 600 is formed on a substrate 602 as described in reference to FIG. 2A. Fins 604 and isolation oxide 610 are formed on the substrate 602, for example as described in reference to FIG. 5A. The SRAM contains a plurality of SRAM cells 642; each SRAM cell 642 includes two driver finFETs 644, two load finFETs 646 and two passgate finFETs 648. Fin heights of the driver finFETs 644, load finFETs 646 and passgate finFETs 648 are substantially equal, as described in reference to FIG. 5A through FIG. 5D. Reliable read and write operations in the SRAM cells 642 require the driver finFETs 644 to have on-state currents which are, for example, 25 percent to 100 percent higher than on-state currents in the passgate finFETs 648. The isolation oxide 610 is thinner in the driver finFETs 644 than in the passgate finFETs 648 so that the passgate finFETs 648 have exposed fin heights which are at least 25 percent lower than exposed fin heights of the driver finFETs 644, which advantageously allows forming the driver finFETs 644 with a single fin 604 for each driver finFET 644. This provides a smaller SRAM area compared to an SRAM in which two fins are required for the driver finFETs to attain the necessary on-state current.
  • Referring to FIG. 6B, gates 612 are formed over the fins 604. The driver finFETs 644, load finFETs 646 and passgate finFETs 648 have one gate 612 each. The gates 612 may be polysilicon gates or may be metal replacement gates. The gates 612 may be formed with uniform width and uniform pitch distances, thereby advantageously providing a reduced area for the SRAM compared with variable gate widths and/or pitch distances to attain the necessary on-state currents in the driver finFETs and passgate finFETs.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments, such as combining embodiments, can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (20)

What is claimed is:
1. An integrated circuit, comprising:
a substrate comprising a semiconductor material;
isolation oxide disposed over the substrate;
a first fin field effect transistor (finFET), comprising:
a first fin of semiconductor material disposed on the substrate, the isolation oxide being disposed adjacent to the first fin, the first fin having a first exposed fin height; and
a first gate disposed over the first fin and extending down sidewalls of the first fin; and
a second finFET, comprising:
a second fin of semiconductor material disposed on the substrate, the isolation oxide being disposed adjacent to the second fin, the second fin having a second exposed fin height, such that the first exposed fin height and the second exposed fin height differ by at least 25 percent; and
a second gate disposed over the second fin and extending down sidewalls of the second fin.
2. The integrated circuit of claim 1, wherein:
a thickness of the isolation oxide adjacent to the first fin and the second fin is substantially uniform; and
a fin height of the first finFET is less than a fin height of the second finFET, the fin height of a fin being a height of a top of the fin above the substrate adjacent to the fin, so that the first exposed fin height is at least 25 percent less than second exposed fin height.
3. The integrated circuit of claim 2, wherein:
the first finFET is a passgate finFET in a static random access memory (SRAM) cell; and
the second finFET is a driver finFET in the SRAM cell.
4. The integrated circuit of claim 1, wherein:
a fin height of the first finFET is substantially equal to a fin height of the second finFET; and
a thickness of the isolation oxide adjacent to the first fin is less than a thickness of the isolation oxide adjacent to the second fin, so that the first exposed fin height is at least 25 percent more than second exposed fin height.
5. The integrated circuit of claim 4, wherein:
the first finFET is a driver finFET in an SRAM cell; and
the second finFET is a passgate finFET in the SRAM cell.
6. The integrated circuit of claim 1, wherein a width of the first fin and a width of the second fin are substantially equal.
7. The integrated circuit of claim 1, wherein pitch distances between centers of the first fin and fins adjacent to the first fin, and pitch distances between centers of the second fin and fins adjacent to the second fin, are all substantially equal.
8. The integrated circuit of claim 1, wherein a width of the first gate and a width of the second gate are substantially equal.
9. The integrated circuit of claim 1, wherein pitch distances between centers of the first gate and gates adjacent to the first gate, and pitch distances between centers of the second gate and gates adjacent to the second gate, are all substantially equal.
10. A method of forming an integrated circuit, comprising the steps of:
providing a substrate comprising a semiconductor material;
forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;
forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;
forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the first fin and covers the second fin;
removing the semiconductor material from a top of the first fin without removing the semiconductor material from a top of the second fin, so that an exposed fin height of the first fin is at least 25 percent less than an exposed fin height of the second fin; and
forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.
11. The method of claim 10, wherein:
the first finFET is a passgate finFET in an SRAM cell; and
the second finFET is a driver finFET in the SRAM cell.
12. The method of claim 10, wherein the first fin and the second fin are formed with substantially equal widths.
13. The method of claim 10, wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances.
14. The method of claim 10, wherein the first gate and the second gate are formed with substantially equal widths.
15. The method of claim 10, wherein the first gate and gates adjacent to the first gate, and the second gate and gates adjacent to the second gate, are formed on substantially equal pitch distances.
16. A method of forming an integrated circuit, comprising the steps of:
providing a substrate comprising a semiconductor material;
forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;
forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;
forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the isolation oxide adjacent to the first fin and covers the isolation oxide adjacent to the second fin;
removing a portion of the isolation oxide from areas exposed by the etch mask, so that an exposed fin height of the first fin is at least 25 percent greater than an exposed fin height of the second fin; and
forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.
17. The method of claim 16, wherein:
the first finFET is a driver finFET in an SRAM cell; and
the second finFET is a passgate finFET in the SRAM cell.
18. The method of claim 16, wherein the first fin and the second fin are formed with substantially equal widths.
19. The method of claim 16, wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances.
20. The method of claim 16, wherein the first gate and the second gate are formed with substantially equal widths.
US14/499,957 2013-12-12 2014-09-29 Design and integration of finfet device Abandoned US20150171217A1 (en)

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EP14869197.5A EP3080835A4 (en) 2013-12-12 2014-12-12 Design and integration of finfet device
PCT/US2014/070116 WO2015089454A1 (en) 2013-12-12 2014-12-12 Design and integration of finfet device
US15/843,629 US20180108564A1 (en) 2013-12-12 2017-12-15 Design and integration of finfet device
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