JP2018511179A - フィードフォワード双方向注入されたスプリットゲートフラッシュメモリセル - Google Patents
フィードフォワード双方向注入されたスプリットゲートフラッシュメモリセル Download PDFInfo
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- 238000002347 injection Methods 0.000 title claims description 10
- 239000007924 injection Substances 0.000 title claims description 10
- 230000002457 bidirectional effect Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 238000005259 measurement Methods 0.000 claims abstract description 13
- 239000007943 implant Substances 0.000 claims description 41
- 238000002513 implantation Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 20
- 238000009826 distribution Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 235000012431 wafers Nutrition 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 208000000044 Amnesia Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 231100000863 loss of memory Toxicity 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
Description
例
Claims (20)
- スプリットゲートフラッシュメモリセル(セル)であって、
半導体表面を有する基板、
第1の浮遊ゲート(FG)上の第1の制御ゲート(CG)及び第2の浮遊ゲート(FG)上の第2のCGであって、各々前記半導体表面上のトンネルゲート誘電体層の上にある、前記第1のCG及び前記第2のCG、
前記第1のFGと前記第2のFGとの間の前記半導体表面における共通ソース又は共通ドレイン、及び
それぞれ、前記半導体表面における第1のBLソース又はドレイン(S/D)と前記第1のFGとの間、及び、前記半導体表面における第2のBL S/Dと前記第2のFGとの間の、選択ゲート誘電体層上の第1の選択ゲート及び第2の選択ゲート、
を含み、
前記第1の選択ゲートが、前記第2の選択ゲートに関連付けられる第2のポケット領域における第2のドーピング分布とは異なる第1のドーピング分布を有する第1のポケット領域を有し、これにより、前記第1の選択ゲートを用いる読み出し電流(Ir)の測定と、前記第2の選択ゲートを用いる前記Irの測定との間の前記セルに対する前記Irにおける変動が低減される、
セル。 - 請求項1に記載のセルであって、前記第1の選択ゲート、前記第2の選択ゲート、前記第1のCG、及び前記第2のCGが、各々ポリシリコンゲートを含む、セル。
- 請求項1に記載のセルであって、前記第1の選択ゲート、前記第2の選択ゲート、前記第1のCG、及び前記第2のCGが、各々金属ゲートを含む、セル。
- 請求項1に記載のセルであって、前記第1のドーピング分布及び前記第2のドーピング分布の総統合ドーズが少なくとも2%異なる、セル。
- 請求項1に記載のセルであって、前記セルが前記半導体表面上に複数あり、前記複数のセルが、共に相互接続され、アレイ状に配置される、セル。
- 請求項1に記載のセルであって、前記セルがnチャネル金属酸化物半導体(MOS)トランジスタを含み、前記第1のポケット領域及び前記第2のポケット領域がいずれもボロンドープされる、セル。
- 請求項1に記載のセルであって、前記基板がシリコンを含む、セル。
- スプリットゲートフラッシュメモリセル(セル)を製造する方法であって、
第1の浮遊ゲート(FG)上の第1の制御ゲート(CG)と、第2のFG上の第2のCGとを含む半導体表面を有する基板であって、前記第1のCG及び第2のCGが各々前記半導体表面上のトンネルゲート誘電体層の上にある、前記基板と、
前記第1のFGと前記第2のFGとの間の前記半導体表面における共通ソース又は共通ドレインと、
それぞれ、前記半導体表面における第1のBLソース又はドレイン(S/D)と前記第1のFGとの間、及び、前記半導体表面における第2のBL S/Dと前記第2のFGとの間の、選択ゲート誘電体層上の第1の選択ゲート及び第2の選択ゲートと、
を提供すること、
前記第1の選択ゲート及び前記第2の選択ゲートの臨界寸法(CD)に基づいて、
第1のドーズを含む第1のポケット注入パラメータのセットと、
第2のドーズを含む第2のポケット注入パラメータとのセットと、
を選択すること、及び
双方向ポケット注入を実施することであって、
前記第1の選択ゲートに関連付けられる第1のポケット領域への前記第1の注入パラメータを用いる第1のポケット注入と、
前記第2の選択ゲートに関連付けられる第2のポケット領域への前記第2の注入パラメータを用いる第2のポケット注入と、
を含む、前記双方向ポケット注入を実施すること、
を含み、
前記第1の注入パラメータ及び前記第2の注入パラメータが異なり、前記第1及び第2のポケット領域における異なるドーパント分布となる差を有しており、これにより、前記第1の選択ゲートを用いる読み出し電流(Ir)の測定と、前記第2の選択ゲートを用いる前記Irの測定との間の、前記セルに対する前記Irにおける変動が低減される、
方法。 - 請求項8に記載の方法であって、前記第1のドーズ及び前記第2のドーズが少なくとも2%異なる、方法。
- 請求項8に記載の方法であって、更に、前記第1の選択ゲートに対する不整合データを前記第1の選択ゲートの前記CDに、及び前記第2の選択ゲートに対する不整合データを前記第2の選択ゲートの前記CDに変換することを含む、方法。
- 請求項8に記載の方法であって、前記第1のポケット注入及び前記第2のポケット注入に対する注入角度が、いずれも15度〜45度である、方法。
- 請求項8に記載の方法であって、前記第1の選択ゲート、前記第2の選択ゲート、前記第1のCG、及び前記第2のCGが、各々ポリシリコンゲートを含む、方法。
- 請求項12に記載の方法であって、更に、前記第1のCG、前記第2のCG、前記第1の選択ゲート、前記第2の選択ゲート、及び前記共通ソース又は共通ドレイン上にシリサイド層を形成することを含む、方法。
- 請求項8に記載の方法であって、前記セルがnチャネル金属酸化物半導体(MOS)トランジスタを含み、前記第1のポケット注入及び前記第2のポケット注入が、いずれもボロン注入を含む、方法。
- 請求項8に記載の方法であって、前記第1の注入パラメータ及び前記第2の注入パラメータの前記差が、前記第1の注入パラメータのための第1の注入ドーズ及び前記第2の注入パラメータのための第2の注入ドーズを備えるドーズ差であり、
前記方法が更に、前記セルを含むダイを有するロットにおける複数のウェハの各々に対して前記ドーズ差をカスタマイズすることを含む、
方法。 - 集積回路(IC)コンビネーションであって、
半導体表面を有する基板、
前記半導体表面上に形成されるプロセッサ、
前記半導体表面上に形成される相互接続されるスプリットゲートフラッシュメモリセル(セル)のアレイであって、各セルが、
第1の浮遊ゲート(FG)上の第1の制御ゲート(CG)及び第2の浮遊ゲート(FG)上の第2のCGであって、各々、前記半導体表面上のトンネルゲート誘電体層の上にある、前記第1のCG及び前記第2のCGと、
前記第1のFGと前記第2のFGとの間の前記半導体表面における共通ソース又は共通ドレインと、
それぞれ、前記半導体表面における第1のBLソース又はドレイン(S/D)と前記第1のFGとの間、及び、前記半導体表面における第2のBL S/Dと前記第2のFGとの間の、選択ゲート誘電体層上の第1の選択ゲート及び第2の選択ゲートと、
を含み、前記第1の選択ゲートが、前記第2の選択ゲートに関連付けられる第2のポケット領域における第2のドーピング分布とは異なる第1のドーピング分布を有する第1のポケット領域を有し、これにより、前記第1の選択ゲートを用いる読み出し電流(Ir)の測定と、前記第2の選択ゲートを用いる前記Irの測定との間の前記セルに対する前記Irにおける変動が低減される、前記セル、及び
相互接続されたセルの前記アレイの、前記プロセッサへの結合のためデータバス、
を含む、ICコンビネーション。 - 請求項16に記載のICコンビネーションであって、前記第1の選択ゲート、前記第2の選択ゲート、前記第1のCG、及び前記第2のCGが、各々ポリシリコンゲートを含む、ICコンビネーション。
- 請求項16に記載のICコンビネーションであって、前記第1のドーピング分布及び前記第2のドーピング分布の総統合ドーズが少なくとも2%異なる、ICコンビネーション。
- 請求項16に記載のICコンビネーションであって、更に、マイクロコントローラユニット(MCU)を含む、ICコンビネーション。
- 請求項16に記載のICコンビネーションであって、前記セルがnチャネル金属酸化物半導体(NMOS)トランジスタを含み、前記第1のポケット領域及び前記第2のポケット領域が、いずれもボロンドープされる、ICコンビネーション。
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