JP2018505553A - 相互接続領域を含む片面電子モジュールの作成方法 - Google Patents
相互接続領域を含む片面電子モジュールの作成方法 Download PDFInfo
- Publication number
- JP2018505553A JP2018505553A JP2017535646A JP2017535646A JP2018505553A JP 2018505553 A JP2018505553 A JP 2018505553A JP 2017535646 A JP2017535646 A JP 2017535646A JP 2017535646 A JP2017535646 A JP 2017535646A JP 2018505553 A JP2018505553 A JP 2018505553A
- Authority
- JP
- Japan
- Prior art keywords
- module
- chip
- metallization
- support
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000001465 metallisation Methods 0.000 claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 25
- 238000005520 cutting process Methods 0.000 claims description 18
- 238000005476 soldering Methods 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 description 24
- 239000000463 material Substances 0.000 description 23
- 239000011248 coating agent Substances 0.000 description 20
- 238000000576 coating method Methods 0.000 description 20
- 238000000151 deposition Methods 0.000 description 14
- 238000004891 communication Methods 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000005304 joining Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000005489 elastic deformation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
- G06K19/07754—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
- G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
- G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Credit Cards Or The Like (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
−連続する誘電支持体又は絶縁支持体の2つの対向面上に、導体トラック又は導電性パッド(又はメタライゼーション)を作成するステップ、
−支持体又はパッド上に少なくとも一つの集積回路チップを搬送して、その裏面を支持体又はパッド上に固定するステップ、
−具体的にははんだめっき線によって、モジュールの外面に配置された導電性接触パッド、及びモジュールの内面に配置された相互接続パッドにチップを接続するステップ、
−チップの周りの被覆領域において、少なくともチップ及び/又はその接続部を保護樹脂で被覆するステップ、
−カード本体に配置されたアンテナに接続するために、これらの相互接続パッドに導電性接合材を堆積させるステップ、
−カード本体内に配置された、具体的には無線周波数アンテナに付属する相互接続端子に接続するために、モジュールを切断して、カード本体の空洞内に搬送するステップ。
−支持体内/支持体上でアクセス可能な第2の回路の端子を有する支持体を形成するステップと、
−モジュールを支持体の上に搬送し、モジュールの第1の回路を第2の回路の当該端子に接続するステップと、を含むことを特徴とする。
当該モジュールは、チップに接続されるとともに、基板の第2の面の上に/第2の面の上方に/第2の面に沿って延出する、電気相互接続要素を具備することを特徴とする。
−連続する誘電支持体又は絶縁支持体の2つの対向面上に、導体トラック又は導電性パッド(又はメタライゼーション)を作成するステップ、
−支持体又はパッド上に少なくとも一つの集積回路チップを搬送して、その裏面を支持体又はパッド上に固定するステップ、
−具体的にははんだめっき線によって、モジュールの外面に配置された導電性接触パッド、及びモジュールの内面に配置された相互接続パッドにチップを接続するステップ、
−チップの周りの被覆領域において、少なくともチップ及び/又はその接続部を保護樹脂で被覆するステップ、
−カード本体に配置されたアンテナに接続するために、これらの相互接続パッドに導電性接合材を堆積させるステップ、
−カード本体内に配置された、具体的には無線周波数アンテナに付属する相互接続端子に接続するために、モジュールを切断して、カード本体の空洞内に搬送するステップ。
−支持体内/支持体上でアクセス可能な第2の回路の端子を有する支持体を形成するステップと、
−モジュールを支持体の上に搬送し、モジュールの第1の回路を第2の回路の当該端子に接続するステップと、を含むことを特徴とする。
当該モジュールは、チップに接続されるとともに、基板の第2の面の上に/第2の面の上方に/第2の面に沿って延出する、電気相互接続要素を具備することを特徴とする。
ここでは、例として、チップは、誘電体の第1の面とは反対側である第2の面と同じ側に配置される。チップは、原則として、はんだめっき線によって接触パッド(又はメタライゼーション)に接続される。
Claims (11)
- 電子チップを有するモジュール(17)の製造方法であって、前記モジュールは、第1の側上でアクセス可能なメタライゼーションと、前記メタライゼーションの前記第1の側とは反対側である第2の側に配置された集積回路チップと、を具備し、前記方法は、前記メタライゼーションから分離して、前記チップに直接接続されるとともに、前記メタライゼーションの前記第2の側に配置される、電気相互接続要素(9C,19C,30)を形成するステップを含むことを特徴とする方法。
- 前記電気相互接続要素(9C,19C)は、前記モジュールの周縁の外側に延出し、後に切断されることを特徴とする、請求項1に記載の方法。
- 前記電気相互接続要素の一端は、はんだ付けの間前記チップ8のピンに直接接続され、他端は、誘電体基板に設けられた開口部(又は接続孔)(22C,22L)を介して、前記モジュールの境界(27)の外側に位置する導電性パッド(又はメタライゼーション)にはんだ付けされることを特徴とする、請求項1又は2に記載の方法。
- 被覆材及び/又は接着剤(14)によって、前記電気相互接続要素(9C,19C,30)の少なくとも一部を除いて、前記チップ(8)を少なくとも部分的に被覆するステップを含むことを特徴とする、請求項1乃至3のいずれか一項に記載の方法。
- 少なくとも1つの前記電気相互接続要素(9C,19C)の一部を捕捉する/一部と電気的に接触するために、前記相互接続領域(Z)内に導電性材料から相互接続ピン(30)を形成するステップを含むことを特徴とする、請求項1乃至4のいずれか一項に記載の方法。
- 帯状体(37)から前記モジュール(17)を取り出す/切り出すステップにおいて、前記電気相互接続要素(9C,19C)を切断するステップを含むことを特徴とする、請求項1乃至5のいずれか一項に記載の方法。
- 電気及び/又は電子装置の製造方法であって、前記装置は、支持体(40)と、請求項1乃至6のいずれか一項に記載の方法によって得られ、前記支持体に固定された前記モジュール(17)とを具備し、前記方法は、
−前記支持体内/前記支持体上でアクセス可能な第2の回路の端子(32)を有する支持体(40)を形成するステップと、
−前記モジュールを前記支持体の上に搬送し、前記モジュールの第1の回路(8,30)を前記第2の回路の前記端子(32)に接続するステップと、
を含むことを特徴とする方法。 - 前記モジュールを接続用の前記端子(32)に接続する前記ステップは、前記モジュール(17)を前記支持体に固定する間に行われ、前記ピン(30)が、前記支持体の接続用の前記端子(32)に接続されることを特徴とする、請求項7に記載の方法。
- 第1の側からアクセス可能なメタライゼーションと、前記メタライゼーションの前記第1の側とは反対側である第2の側に配置された集積回路チップとを具備する、電子チップを有するモジュール(17)であって、前記メタライゼーションから分離して、前記チップに直接接続されるとともに、前記メタライゼーションの前記第2の側に配置される、電気相互接続要素(9C,19C,30)を具備することを特徴とするモジュール。
- 誘電体基板(20)の第1の面上でアクセス可能な電気接触パッド(10)と、前記第1の面とは反対側である第2の面と同じ側に位置する集積回路チップ(8)とを具備する、請求項9に記載の電子チップを有するモジュール(17)であって、
前記チップに接続されるとともに、前記誘電体基板の前記第2の面の上に/前記第2の面の上方に/前記第2の面に沿って延出する、電気相互接続要素(9C,19C,30)を具備することを特徴とする、モジュール。 - 請求項9又は10に記載のモジュールを具備する装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP15305271.7A EP3059698B1 (fr) | 2015-02-20 | 2015-02-20 | Procédé de fabrication d'un module électronique simple face comprenant des zones d'interconnexion |
EP15305271.7 | 2015-02-20 | ||
PCT/EP2016/052744 WO2016131682A1 (fr) | 2015-02-20 | 2016-02-09 | Procede de fabrication d'un module electronique simple face comprenant des zones d'interconnexion |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018232327A Division JP6756805B2 (ja) | 2015-02-20 | 2018-12-12 | 相互接続領域を含む片面電子モジュールの作成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018505553A true JP2018505553A (ja) | 2018-02-22 |
JP6453472B2 JP6453472B2 (ja) | 2019-01-16 |
Family
ID=52648959
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017535646A Active JP6453472B2 (ja) | 2015-02-20 | 2016-02-09 | 相互接続領域を含む片面電子モジュールの作成方法 |
JP2018232327A Active JP6756805B2 (ja) | 2015-02-20 | 2018-12-12 | 相互接続領域を含む片面電子モジュールの作成方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018232327A Active JP6756805B2 (ja) | 2015-02-20 | 2018-12-12 | 相互接続領域を含む片面電子モジュールの作成方法 |
Country Status (13)
Country | Link |
---|---|
US (1) | US10282652B2 (ja) |
EP (2) | EP3059698B1 (ja) |
JP (2) | JP6453472B2 (ja) |
KR (1) | KR102014621B1 (ja) |
CN (1) | CN107111779B (ja) |
AU (1) | AU2016221971B2 (ja) |
CA (1) | CA2968070C (ja) |
ES (1) | ES2867102T3 (ja) |
MX (1) | MX2017006130A (ja) |
PL (1) | PL3059698T3 (ja) |
SG (1) | SG11201703935TA (ja) |
WO (1) | WO2016131682A1 (ja) |
ZA (1) | ZA201703296B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3047101B1 (fr) | 2016-01-26 | 2022-04-01 | Linxens Holding | Procede de fabrication d’un module de carte a puce et d’une carte a puce |
FR3113324B1 (fr) | 2020-08-04 | 2024-05-24 | Smart Packaging Solutions | Module electronique pour carte contenant au moins une antenne et son procede de fabrication |
KR20220032181A (ko) * | 2020-09-07 | 2022-03-15 | 엘지이노텍 주식회사 | 회로 기판 및 이를 포함하는 지문인식용 스마트 카드 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08107123A (ja) * | 1994-10-04 | 1996-04-23 | Hitachi Ltd | 半導体集積回路装置の製造方法、その製造装置および半導体集積回路装置 |
JP2011170525A (ja) * | 2010-02-17 | 2011-09-01 | Toshiba Corp | カード基材及びこのカード基材を有するicカード |
JP2012043341A (ja) * | 2010-08-23 | 2012-03-01 | Toppan Printing Co Ltd | Icモジュールおよびそれを用いたicカード |
US20120193436A1 (en) * | 2011-01-31 | 2012-08-02 | American Bank Note Company | Dual-interface smart card |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2716281B1 (fr) | 1994-02-14 | 1996-05-03 | Gemplus Card Int | Procédé de fabrication d'une carte sans contact. |
FR2784210B1 (fr) * | 1998-10-02 | 2001-09-14 | Gemplus Card Int | Carte a puce sans contact comportant des moyens d'inhibition |
EP2420960A1 (fr) | 2010-08-17 | 2012-02-22 | Gemalto SA | Procédé de fabrication d'un dispositif électronique comportant un module indémontable et dispositif obtenu |
EP2575086A1 (fr) * | 2011-09-27 | 2013-04-03 | Gemalto SA | Procédé de connexion d'un microcircuit à des zones conductrices noyées dans un support |
FR2998395B1 (fr) | 2012-11-21 | 2016-01-01 | Smart Packaging Solutions Sps | Module electronique simple face pour carte a puce a double interface de communication |
EP2736001A1 (fr) * | 2012-11-27 | 2014-05-28 | Gemalto SA | Module électronique à interface de communication tridimensionnelle |
-
2015
- 2015-02-20 EP EP15305271.7A patent/EP3059698B1/fr active Active
- 2015-02-20 ES ES15305271T patent/ES2867102T3/es active Active
- 2015-02-20 EP EP21158480.0A patent/EP3869409A1/fr not_active Withdrawn
- 2015-02-20 PL PL15305271T patent/PL3059698T3/pl unknown
-
2016
- 2016-02-09 MX MX2017006130A patent/MX2017006130A/es unknown
- 2016-02-09 US US15/531,159 patent/US10282652B2/en active Active
- 2016-02-09 KR KR1020177015859A patent/KR102014621B1/ko active IP Right Grant
- 2016-02-09 CA CA2968070A patent/CA2968070C/fr active Active
- 2016-02-09 CN CN201680004744.8A patent/CN107111779B/zh active Active
- 2016-02-09 JP JP2017535646A patent/JP6453472B2/ja active Active
- 2016-02-09 WO PCT/EP2016/052744 patent/WO2016131682A1/fr active Application Filing
- 2016-02-09 SG SG11201703935TA patent/SG11201703935TA/en unknown
- 2016-02-09 AU AU2016221971A patent/AU2016221971B2/en active Active
-
2017
- 2017-05-12 ZA ZA2017/03296A patent/ZA201703296B/en unknown
-
2018
- 2018-12-12 JP JP2018232327A patent/JP6756805B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08107123A (ja) * | 1994-10-04 | 1996-04-23 | Hitachi Ltd | 半導体集積回路装置の製造方法、その製造装置および半導体集積回路装置 |
JP2011170525A (ja) * | 2010-02-17 | 2011-09-01 | Toshiba Corp | カード基材及びこのカード基材を有するicカード |
JP2012043341A (ja) * | 2010-08-23 | 2012-03-01 | Toppan Printing Co Ltd | Icモジュールおよびそれを用いたicカード |
US20120193436A1 (en) * | 2011-01-31 | 2012-08-02 | American Bank Note Company | Dual-interface smart card |
Also Published As
Publication number | Publication date |
---|---|
ZA201703296B (en) | 2019-06-26 |
US10282652B2 (en) | 2019-05-07 |
JP6453472B2 (ja) | 2019-01-16 |
KR102014621B1 (ko) | 2019-08-26 |
KR20170081693A (ko) | 2017-07-12 |
AU2016221971A1 (en) | 2017-07-20 |
JP6756805B2 (ja) | 2020-09-16 |
CA2968070C (fr) | 2021-05-11 |
CN107111779A (zh) | 2017-08-29 |
CA2968070A1 (fr) | 2016-08-25 |
JP2019071435A (ja) | 2019-05-09 |
EP3869409A1 (fr) | 2021-08-25 |
CN107111779B (zh) | 2020-09-15 |
PL3059698T3 (pl) | 2021-10-25 |
WO2016131682A1 (fr) | 2016-08-25 |
MX2017006130A (es) | 2018-02-09 |
SG11201703935TA (en) | 2017-06-29 |
BR112017015014A2 (pt) | 2018-01-23 |
US20170372186A1 (en) | 2017-12-28 |
ES2867102T3 (es) | 2021-10-20 |
EP3059698B1 (fr) | 2021-03-31 |
AU2016221971B2 (en) | 2019-01-31 |
EP3059698A1 (fr) | 2016-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6568600B1 (en) | Chip card equipped with a loop antenna, and associated micromodule | |
JP4631910B2 (ja) | アンテナ内蔵型記憶媒体 | |
US8348171B2 (en) | Smartcard interconnect | |
JP6756805B2 (ja) | 相互接続領域を含む片面電子モジュールの作成方法 | |
US10366320B2 (en) | Dual-interface IC card | |
JPH0744239B2 (ja) | チツプ・キヤリアと集積半導体チツプを有するモジユール | |
US20180300597A1 (en) | Method for embedding integrated circuit flip chip | |
ES2904617T3 (es) | Métodos de fabricación de tarjetas con chip y soportes de antena para tarjetas con chip | |
US20170249545A1 (en) | Chip Card Manufacturing Method, and Chip Card Obtained by Said Method | |
CN108496187B (zh) | 用于制造芯片卡模块的方法和芯片卡 | |
JP7474251B2 (ja) | チップカード用電子モジュール | |
US20040159932A1 (en) | Semiconductor device | |
JP3572216B2 (ja) | 非接触データキャリア | |
JP2009075782A (ja) | Icモジュール及びicカード | |
JP4684433B2 (ja) | 接触・非接触兼用型icモジュールとその製造方法 | |
BR112017015014B1 (pt) | Método para fabricar um módulo tendo um chip eletrônico, método para fabricar um dispositivo elétrico e/ou eletrônico, e dispositivo | |
WO2024196307A1 (en) | Articles of manufacture relating to ic modules and smart cards | |
EP3079105B1 (en) | Dual-interface ic card components and method for manufacturing the dual-interface ic card components | |
KR20210060476A (ko) | 휴대용 오브젝트용 전자 모듈을 제조하기 위한 방법 | |
JP2004227331A (ja) | Icカードおよびその製造方法 | |
JP2010238081A (ja) | Icカード及び通信装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180403 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180620 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180828 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181012 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181109 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20181120 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20181212 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6453472 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |