JP2018207110A5 - - Google Patents

Download PDF

Info

Publication number
JP2018207110A5
JP2018207110A5 JP2018108626A JP2018108626A JP2018207110A5 JP 2018207110 A5 JP2018207110 A5 JP 2018207110A5 JP 2018108626 A JP2018108626 A JP 2018108626A JP 2018108626 A JP2018108626 A JP 2018108626A JP 2018207110 A5 JP2018207110 A5 JP 2018207110A5
Authority
JP
Japan
Prior art keywords
metal
feature
concave
isolated
concave feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018108626A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018207110A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JP2018207110A publication Critical patent/JP2018207110A/ja
Publication of JP2018207110A5 publication Critical patent/JP2018207110A5/ja
Priority to JP2023025336A priority Critical patent/JP7492618B2/ja
Pending legal-status Critical Current

Links

JP2018108626A 2017-06-06 2018-06-06 二重金属電力レールを有する集積回路の製造方法 Pending JP2018207110A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023025336A JP7492618B2 (ja) 2017-06-06 2023-02-21 二重金属電力レールを有する集積回路の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762515968P 2017-06-06 2017-06-06
US62/515,968 2017-06-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023025336A Division JP7492618B2 (ja) 2017-06-06 2023-02-21 二重金属電力レールを有する集積回路の製造方法

Publications (2)

Publication Number Publication Date
JP2018207110A JP2018207110A (ja) 2018-12-27
JP2018207110A5 true JP2018207110A5 (enExample) 2021-07-26

Family

ID=64458995

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018108626A Pending JP2018207110A (ja) 2017-06-06 2018-06-06 二重金属電力レールを有する集積回路の製造方法
JP2023025336A Active JP7492618B2 (ja) 2017-06-06 2023-02-21 二重金属電力レールを有する集積回路の製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2023025336A Active JP7492618B2 (ja) 2017-06-06 2023-02-21 二重金属電力レールを有する集積回路の製造方法

Country Status (3)

Country Link
US (1) US10580691B2 (enExample)
JP (2) JP2018207110A (enExample)
KR (1) KR102694691B1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879115B2 (en) * 2017-11-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
US11121075B2 (en) * 2018-03-23 2021-09-14 Qualcomm Incorporated Hybrid metallization interconnects for power distribution and signaling
US11101175B2 (en) * 2018-11-21 2021-08-24 International Business Machines Corporation Tall trenches for via chamferless and self forming barrier
US11024537B2 (en) * 2019-08-09 2021-06-01 Applied Materials, Inc. Methods and apparatus for hybrid feature metallization
KR102833584B1 (ko) * 2019-09-03 2025-07-15 삼성전자주식회사 반도체 소자
US11450562B2 (en) * 2019-09-16 2022-09-20 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11908738B2 (en) 2021-10-18 2024-02-20 International Business Machines Corporation Interconnect including integrally formed capacitor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
KR20010017237A (ko) * 1999-08-09 2001-03-05 박종섭 Ｍｍｌ반도체소자의 아날로그 커패시터형성방법
JP2002353161A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
KR100447977B1 (ko) * 2002-03-13 2004-09-10 주식회사 하이닉스반도체 듀얼 다마신 공정을 이용한 반도체 소자의 금속 배선 형성방법
JP2004063995A (ja) * 2002-07-31 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
US8093716B2 (en) * 2005-07-29 2012-01-10 Texas Instruments Incorporated Contact fuse which does not touch a metal layer
JP2007081113A (ja) * 2005-09-14 2007-03-29 Sony Corp 半導体装置の製造方法
US7544608B2 (en) * 2006-07-19 2009-06-09 International Business Machines Corporation Porous and dense hybrid interconnect structure and method of manufacture
KR20080029251A (ko) * 2006-09-28 2008-04-03 주식회사 하이닉스반도체 플래시 메모리 소자 제조방법
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
JP5820416B2 (ja) * 2013-03-22 2015-11-24 株式会社東芝 半導体装置及びその製造方法
US9837354B2 (en) * 2014-07-02 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid copper structure for advance interconnect usage
KR102310404B1 (ko) * 2015-11-05 2021-10-07 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9805976B2 (en) * 2016-01-08 2017-10-31 Applied Materials, Inc. Co or Ni and Cu integration for small and large features in integrated circuits

Similar Documents

Publication Publication Date Title
JP2018207110A5 (enExample)
US9378972B2 (en) Integration of dense and variable pitch fin structures
CN105244370B (zh) 金属栅极结构与其制作方法
CN109585305A (zh) 一种形成半导体器件的方法
CN103579007B (zh) 用于鳍式场效应晶体管器件的后栅极隔离区域形成方法
JP2016149546A5 (enExample)
CN106158600A (zh) 迭代自对准图案化
JP2019510366A5 (enExample)
US20080050900A1 (en) Methods for pitch reduction formation
JP2016046530A5 (ja) 半導体装置の作製方法
JP2020520125A (ja) 高度なパターン形成用途のためのインサイチュでの選択的堆積及びエッチング
JP2021101470A (ja) エッチング及び選択的除去の向上のためのハードマスク膜の化学的修飾
CN104067343A (zh) 制造器件的方法
US9679994B1 (en) High fin cut fabrication process
KR20190101307A (ko) 60nm 이하 mram 디바이스용 극대 높이 최상 전극을 규정하기 위한 금속/유전체/금속 하이브리드 하드 마스크
CN106910708A (zh) 具有局部互连结构的器件及其制造方法
US8906244B2 (en) Method for forming a device having nanopillar and cap structures
TW201605055A (zh) 在移除控制閘極期間使用流動材料以形成字元線端的半導體裝置及其製造方法
CN103943469A (zh) 一种图形自对准形成方法
CN104701184A (zh) 形成多鳍结构场发射晶体管的方法
JP2018528621A5 (enExample)
CN105990223B (zh) 一种形成超低介电常数介质层的方法
CN105977150A (zh) 减少ono刻蚀中衬底表面损伤的方法以及半导体制造方法
CN104022063B (zh) 浅槽的形成方法
CN107437501A (zh) 一种栅极结构及其制造方法