CN105244370B - 金属栅极结构与其制作方法 - Google Patents
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 173
- 239000002184 metal Substances 0.000 title claims abstract description 173
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 24
- 229920006254 polymer film Polymers 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000011265 semifinished product Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 21
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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Abstract
本发明公开一种金属栅极结构与其制作方法,其金属栅极结构包含一基底,基底划分为一密集区域和一宽疏区域,一第一金属栅极结构设置于密集区域,第一金属栅极结构包含一第一沟槽设于密集区域,一第一金属层设于第一沟槽中,一第二金属栅极结构设置于宽疏区域,第二金属栅极结构包含一第二沟槽设于宽疏区域中以及一第二金属层设于第二沟槽中,其中第二金属层的高度较第一金属层的高度大。
Description
技术领域
本发明涉及一种金属栅极结构与其制作方法,特别是涉及一种形成宽疏区域的金属栅极较密集区域的金属栅极高的结构及其制作方法。
背景技术
随着集成电路领域的快速发展,高效能、高集成度、低成本、轻薄短小已成为电子产品设计制造上所追寻的目标。对目前的半导体产业而言,为了符合上述目标,往往需要在同一芯片上,制造出多种功能的元件。换言之,在同一芯片上,同一层材料层的不同区块上,所形成的图案密度会有高低不同的情形。
然而,以蚀刻作为图案化的方法时,往往会因为图案密度的差异而导致蚀刻速率的不平均。在图案密度大,也就是设置小尺寸图案的密集区域,每单位表面积接受到较少的蚀刻剂,蚀刻速率会比较慢;在图案密度小,也就是设置大寸图案的宽疏区域,每单位表面积接受到较多的蚀刻剂,蚀刻速率则会比较快,此种情形称为微负载效应,此微负载效应将导致在密集区域和在宽疏区域的材料层被蚀刻的深度不一致,最后使得在密集区域的材料层高度较宽疏区域的材料层高,甚至在宽疏区域的材料层也会因为被过度蚀刻使得前层的材料层被曝露出来。
如此一来,不但会影响元件整体的均一性,也会增加后续制作工艺的复杂度。
发明内容
有鉴于此,本发明的目的在于提出一种金属栅极结构的制作方法,可以形成宽疏区域的金属栅极较密集区域的金属栅极高的结构。
为达上述目的,根据本发明的第一优选实施例,一种金属栅极结构的制作方法,前述制作方法应用于一金属栅极结构的半成品,前述半成品包含一基底包含一密集区域和一宽疏区域,一介电层覆盖基底的密集区域和宽疏区域,一第一沟槽设于密集区域的介电层中,一第一栅极介电层、一第一材料层和一第一金属层设于第一沟槽中,第一栅极介电层接触基底,第一材料层位于第一金属层和第一栅极介电层之间,其中第一材料层呈U型,并且具有一第一垂直侧边,此外,第一金属层、第一栅极介电层、第一材料层和介电层彼此切齐,第二金属层、第二栅极介电层、第二材料层和介电层彼此切齐,本发明的金属栅极结构的制作工艺包含以下步骤:
步骤(a):移除部分的第一材料层的第一垂直侧边。
步骤(b):在移除部分的第一垂直侧边之后,移除部分的第一金属层使得第一金属层的一上表面和第一垂直侧边的一上表面切齐。
步骤(d):移除部分的第一栅极介电层,使第一栅极介电层的一上表面和第一垂直侧边的上表面切齐。
根据本发明的第二优选实施例,一种金属栅极结构,包含:一基底包含一密集区域和一宽疏区域,一第一金属栅极结构设置于密集区域,第一金属栅极结构包含一第一沟槽设于密集区域,一第一金属层设于第一沟槽中,一第二金属栅极结构设置于宽疏区域,第二金属栅极结构包含一第二沟槽设于宽疏区域以及一第二金属层设于第二沟槽中,其中第二金属层的高度较第一金属层的高度大。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1至图9为本发明的优选实施例绘示的是本发明金属栅极结构的制作方法。
符号说明
10 基底 11 上表面
12 虚置栅极 14 蚀刻停止层
16 介电层 18 第一沟槽
20 第一栅极介电层 22 第一材料层
24 第一金属层 26 第一金属栅极结构的半成品
28 上表面 30 第一垂直侧边
32 第一高分子薄膜 34 上表面
36 上表面 38 第一帽盖层
100 第一金属栅极结构 118 第二沟槽
120 第二栅极介电层 122 第二材料层
124 第二金属层 126 第二金属栅极结构的半成品
128 上表面 130 第二垂直侧边
132 第二高分子薄膜 134 上表面
136 上表面 138 第二帽盖层
200 第二金属栅极结构
具体实施方式
图1至图9为根据本发明的优选实施例绘示的是本发明金属栅极结构的制作方法。如图1所示,首先提供一基底10,基底10上定义有一宽疏区域A和一密集区域B,在宽疏区域A设置的元件图案密度小,也就是在宽疏区域A中总共的元件尺寸除以宽疏区域A的面积所得的值较小;在密集区域B的元件图案密度大,也就是在密集区域B中总共的元件尺寸除以密集区域B的面积所得的值较大。基底10可以一硅基底、一锗基底、一砷化镓基底、一硅锗基底、一硅覆绝缘基底或是其它适合的材料,此外,基底10可以为一鳍状结构或者一平面结构。接着在基底10上的宽疏区域A和密集区域B内分别形成至少一虚置栅极12,之后形成一间隙壁(图未示)虚置栅极12的两侧,然后选择性地形成一蚀刻停止层14顺应地覆盖前述的虚置栅极12,之后再形成一介电层16全面覆盖宽疏区域A和密集区域B,接着蚀刻介电层16直至曝露出宽疏区域A和密集区域B的虚置栅极12。
如图2所示,移除在宽疏区域A和密集区域B的虚置栅极12,移除虚置栅极12后在介电层16中的密集区域B和宽疏区域A分别形成一第一沟槽18和一第二沟槽118,之后依序在第一沟槽18中填入第一栅极介电层20、第一材料层22和第一金属层24,此外也在第二沟槽118中填入第二栅极介电层120、第二材料层122和第二金属层124。第一栅极介电层20和第二栅极介电层120可以高介电常数介电层,例如氧化铪(hafnium oxide,HfO2)、氧化锆(zirconium oxide,ZrO2)等或是其它适合的介电材料。第一材料层22可以包含功函数层、阻障层或其组合;第二材料层122可以包含功函数层、阻障层或其组合。功函数层可以为一氮化铝金属层、一氮化钛金属层或其他金属层,其材质的选用由之后所要形成的晶体管是P型或N型而定,举例来说,当晶体管是P型时功函数层可为一氮化钛金属层;而当晶体管是N型时功函数层可为一氮化铝金属层。阻障层用来来防止各材料层之间因材质中的成分扩散而相互污染。在一实施例中,阻障层例如为一氮化钛层、一氮化钽层或由氮化钛层及氮化钽层所组成的复合结构层,但本发明不以此为限。此外,第一金属层24和第二金属层124可以独立地选自铝、钨或其它适合的金属或合金。视不同的产品需求,第一栅极介电层20和第二栅极介电层120可以为相同或不同材料,第一材料层22和第二材料层122可以为相同或不同材料,第一金属层24和第二金属层124可以为相同或不同材料,第一栅极介电层20和第二栅极介电层120若为相同材料则可以在同一步骤形成,同样地第一材料层22和第二材料层122若为相同材料也可以在同一步骤形成,第一金属层24和第二金属124若为相同材料也可以在同一步骤形成。
如图3所示,平坦化第一金属层24、第二金属层124、第一材料层22、第二材料层122、第一栅极介电层20和第二栅极介电层120,直至介电层16曝露出来,至此形成一第一金属栅极结构的半成品26以及一第二金属栅极结构的半成品126。此时第一金属层24和第二金属层等高124,并且第一金属层24、第一栅极介电层20、第一材料层22和介电层16彼此切齐,第二金属层124、第二栅极介电层120、第二材料层122和介电层16彼此切齐。
此外,第一金属层24的上表面28至基底10的上表面11定义为第一金属层24的高度H1,第二金属层124的一上表面128至基底10的上表面11定义为第二金属层124的高度H2,高度H1和高度H2相同。此外,在本实施中,第二金属层124的宽度W2较该第一金属层24的宽度W1大,然而在另外的实施例中,也可以是第二金属层124的宽度W2较该第一金属层24的宽度W1小的情形。另外,此时第一材料层22和第二材料层122都呈U型,第一材料层22具有一第一垂直侧边30,第二材料层122具有一第二垂直侧边130。第一栅极介电层20和第二栅极介电层120也呈U型。
如图4所示,进行一第一蚀刻步骤,利用一干蚀刻同时非等向移除部分的第一垂直侧边30和部分的第二垂直侧边130,根据本发明的一优选实施例,干蚀刻的蚀刻剂可以为Cl2/BCl3/O2的混合物。在进行干蚀刻时,在第一金属层24和第二金属层124上分别会形成一第一高分子薄膜32和一第二高分子薄膜132,第二高分子薄膜132较第一高分子薄膜32厚,第一高分子薄膜32和第二高分子薄膜132由蚀刻残留物所构成。
如图5所示,进行一第二蚀刻步骤,再利用另一干蚀刻同时非等向移除部分的第一金属层24和部分的第二金属层124,直至第一金属层24的上表面28和第一垂直侧边30的上表面34切齐,在移除部分的第一金属层24和部分的第二金属层124之前,需先蚀刻去除第一高分子薄膜32和第二高分子薄膜132,才能蚀刻到第一金属层24和第二金属层124,由于第二高分子薄膜132较厚,因此蚀刻时会第一高分子薄膜32会先消耗掉,失去第一高分子薄膜32后,第一金属层24会比第二金属层124先开始被蚀刻,最后,在第二蚀刻步骤结束后,第一金属层24被蚀刻的厚度就会较第二金属层124被蚀刻的厚度大。此时第二金属层124由高度H2变成高度H2’,而第一金属层24由高度H1变成高度H1’,此时第二金属层124的高度H2’较第一金属层24的高度H1’大。第一金属层24的上表面28至基底10的上表面11定义为第一金属层24的高度H1’,第二金属层124的一上表面128至基底10的上表面11定义为第二金属层124的高度H2’。此外,第二金属层124的上表面128较第二垂直侧边130的上表面134高,第二蚀刻步骤的蚀刻剂可以为Cl2/O2/N2/NF3/SiCl4的混合物。
之后检查第一金属层24的高度H1’是否已到达一预定高度,第一金属层24的宽度W1配合第一金属层24的预定高度,可使得第一金属层24具有一适当的电阻值。若是已到达,则进行移除栅极介电层的步骤。若还未达前述预定高度,则重复进行第一蚀刻步骤和第二蚀刻步骤,直至第一金属层24的高度H1’到达预定高度,第一蚀刻步骤和第二蚀刻步骤重复的次数不限。举例而言,如图6所示,当第一金属层24的高度H1’未达预定高度时,则再度进行第一蚀刻步骤,利用干蚀刻同时非等向移除部分的第一垂直侧边30和部分的第二垂直侧边130,同样地,蚀刻过程中也会形成第一高分子薄膜32和第二高分子薄膜132,关于此步骤的详细叙述,请参考前文对于图4的描述,在此不再赘述。
之后如图7所示,再度进行第二蚀刻步骤,利用另一干蚀刻同时非等向移除部分的第一金属层24和部分的第二金属层124,直至第一金属层24的上表面28和第一垂直侧边30的上表面34切齐,此时第二金属层124由高度H2’变成高度H2”,而第一金属层24由高度H1’变成高度H1”,第二金属层124的高度H2”较第一金属层24的高度H1”。第一金属层24的上表面28至基底10的上表面11定义为第一金属层24的高度H1”,第二金属层124的一上表面128至基底10的上表面11定义为第二金属层124的高度H2”。关于此步骤的详细叙述,请参考前文对于图5的描述,在此不再赘述。
此时检查第一金属层24的高度H1”是否已到达一预定高度。在本实施中,假设已到第一金属层24的高度H1”已到达预定高度,则进行移除栅极介电层的步骤,如图8所示,先利用干蚀刻同时移除部分的第一栅极介电层20和第二栅极介电层120,使得第一栅极介电层20的上表面36和第一垂直侧边30的上表面34切齐,并且第二栅极介电层120的上表面136和第二垂直侧边130的上表面134切齐,在本步骤的蚀刻剂可以为Cl2/BCl3的混合物。之后为确保在第一垂直侧边30的上表面34之上的第一栅极介电层20以及在第二垂直侧边130的上表面134之上的第二栅极介电层120被完全移除,可选择性地利用稀释的氢氟酸清洗第一栅极介电层20和第二栅极介电层120。
然后如图9所示,分别形成一材料层(图未示)于第一金属层24和第二金属层124上,之后进行化学研磨步骤,使得材料层和介电层16彼此切齐,以形成一第一帽盖层38和一第二帽对层138于第一金属层24和第二金属层124上,至此本发明的第一金属栅极结构100和第二金属栅极结构200业已完成。
请参阅图9,根据本发明的一优选实施例,本发明的金属栅极结构,包含:一基底10其上定义有密集区域B和宽疏区域A,一介电层16覆盖基底的密集区域B和宽疏区域A,一第一金属栅极结构100设置于密集区域B,一第二金属栅极结构200设置于宽疏区域A。第一金属栅极结构200包含一第一沟槽18设于密集区域B的介电层16中,一第一栅极介电层20、一第一材料层22和一第一金属层24设于第一沟槽18中,第一栅极介电层20接触基底10,第一材料层22位于第一金属层24和第一栅极介电层20之间,且第一材料层22为U型并且第一材料层22具有一第一垂直侧边30。第二金属栅极结构200包含一第二沟槽118设于宽疏区域A的介电层16中,一第二栅极介电层120、一第二材料层122和一第二金属层124设于第二沟槽118中,第二栅极介电层120接触基底10,一第二材料层122位于第二金属层124和第二栅极介电层120之间,且第二材料层122为U型并且第二材料层122具有一第二垂直侧边130。此外,在第一栅极介电层20和介电层16之间以及第二栅极介电层120和介电层16之间,可以选择性设置一蚀刻停止层14。一第一帽盖层38覆盖第一金属层24,一第二帽盖层138覆盖第二金属层124。第二金属层124的宽度W2较该第一金属层24的宽度W1大。基底10可以一硅基底、一锗基底、一砷化镓基底、一硅锗基底、一硅覆绝缘基底或是其它适合的材料,此外,基底10可以为一鳍状结构或者一平面结构。第一栅极介电层20和第二栅极介电层120可以高介电常数介电层,例如氧化铪(hafnium oxide,HfO2)、氧化锆(zirconium oxide,ZrO2)等或是其它适合的介电材料。第一材料层22可以包含功函数层、阻障层或其组合;第二材料层120可以包含功函数层、阻障层或其组合。功函数层可以为一氮化铝金属层、一氮化钛金属层或其他金属层,其材质的选用由之后所要形成的晶体管是P型或N型而定,举例来说,当晶体管是P型时功函数层可为一氮化钛金属层;而当晶体管是N型时功函数层可为一氮化铝金属层。阻障层用来来防止各材料层之间因材质中的成分扩散而相互污染。在一实施例中,阻障层例如为一氮化钛层、一氮化钽层或由氮化钛层及氮化钽层所组成的复合结构层,但本发明不以此为限。此外,第一金属层24和第二金属层124可以独立地选自铝、钨或其它适合的金属或合金。视不同的产品需求,第一栅极介电层20和第二栅极介电层120可以为相同或不同材料,第一材料层22和第二材料层122可以为相同或不同材料,第一金属层24和第二金属层124可以为相同或不同材料。第一金属层24的上表面28至基底10的上表面11定义为第一金属层24的高度H1”,第二金属层124的一上表面128至基底10的上表面11定义为第二金属层124的高度H2”,值得注意的是:第二金属层124的高度H2”较第一金属层24的高度H1”大,此外,第二垂直侧边130的一上表面134较第一材料层30的一上表面34高,第一金属层24的上表面28和第一垂直侧边30的上表面34切齐,第一栅极介电层20的上表面36和第一垂直侧边30的上表面34切齐,并且第二栅极介电层120的上表面136和第二垂直侧边130的上表面134切齐。
本发明的金属栅极结构的制作方法,使得在宽疏区域的金属栅极的高度大于在密集区域的金属栅极,由于制作工艺的参数以密集区域的金属栅极的高度来计算,只要确保密集区域的金属栅极达到一预定高度,就可以保证宽疏区域的金属栅极不会被过度蚀刻,因此可有效避免传统制作工艺过度蚀刻宽疏区域的金属栅极而使得前层的材料层曝露出来的问题。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (11)
1.一种金属栅极结构的制作方法,该制作方法应用于一金属栅极结构的半成品,该半成品包含一基底,该基底包含一密集区域和一宽疏区域,一介电层覆盖该基底的该密集区域和该宽疏区域,一第一沟槽设于该密集区域的该介电层中,一第一栅极介电层、一第一材料层和一第一金属层设于该第一沟槽中,该第一栅极介电层接触该基底,该第一材料层位于该第一金属层和该第一栅极介电层之间,其中该第一材料层呈U型,并且具有一第一垂直侧边,第二沟槽设于该宽疏区域的该介电层中;以及第二栅极介电层、第二材料层和第二金属层,设于该第二沟槽中,该第二栅极介电层接触该基底,该第二材料层位于该第二金属层和该第二栅极介电层之间,其中该第二材料层呈U型,并且具有第二垂直侧边,该金属栅极结构的制作工艺包含以下步骤:
步骤(a):利用干蚀刻移除部分的该第一材料层的该第一垂直侧边和部分的该第二垂直侧边,并且同时在该第一金属层和该第二金属层上分别形成一第一高分子薄膜和一第二高分子薄膜,该第二高分子薄膜较该第一高分子薄膜厚;
步骤(b):在移除部分的该第一垂直侧边和该第二垂直侧边之后,移除部分的该第一金属层和部分的该第二金属层,使得该第一金属层的一上表面和该第一垂直侧边的一上表面切齐,其中,在移除部分的该第一金属层和部分的该第二金属层之前,先同时蚀刻去除该第一高分子薄膜和该第二高分子薄膜;
步骤(d):移除部分的该第一栅极介电层,使该第一栅极介电层的一上表面和该第一垂直侧边的该上表面切齐。
2.如权利要求1所述的金属栅极结构的制作方法,还包含:
步骤(c):重复步骤(a)和步骤(b)至该第一金属层达到一预定高度。
3.如权利要求1所述的金属栅极结构的制作方法,其中步骤(d)还包含以下步骤:在移除部分的该第一栅极介电层时,同时移除部分的该第二栅极介电层,使该第二栅极介电层的一上表面和该第二垂直侧边的一上表面切齐。
4.如权利要求3所述的金属栅极结构的制作方法,还包含:
步骤(c):重复步骤(a)和步骤(b)至该第一金属层达到一预定高度。
5.如权利要求3所述的金属栅极结构的制作方法,还包含:在进行步骤(d)之后,以稀释的氢氟酸清洗该第一栅极介电层和该第二栅极介电层。
6.如权利要求4所述的金属栅极结构的制作方法,其中在进行步骤(c)之后,该第二金属层的高度较该第一金属的高度大。
7.如权利要求3所述的金属栅极结构的制作方法,其中在进行步骤(b)之后,该第二金属层的高度较该第一金属层的高度大。
8.如权利要求1所述的金属栅极结构的制作方法,其中该第二金属层的宽度较该第一金属层的宽度大。
9.如权利要求1所述的金属栅极结构的制作方法,其中该第一栅极介电层和该第二栅极介电层利用相同步骤以相同材料制作,该第一金属层和该第二金属层利用相同步骤以相同材料制作。
10.如权利要求1所述的金属栅极结构的制作方法,其中该第一材料层包含第一阻障层和第一功函数层。
11.如权利要求1所述的金属栅极结构的制作方法,还包含分别形成一第一帽盖层和一第二帽盖层于该第一金属层和该第二金属层,以完成该金属栅极结构。
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US9818841B2 (en) * | 2015-05-15 | 2017-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with unleveled gate structure and method for forming the same |
US9583485B2 (en) * | 2015-05-15 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same |
CN106531776B (zh) * | 2015-09-11 | 2021-06-29 | 联华电子股份有限公司 | 半导体结构 |
US9824920B2 (en) * | 2016-04-04 | 2017-11-21 | Globalfoundries Inc. | Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices |
US9929271B2 (en) * | 2016-08-03 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10043713B1 (en) * | 2017-05-10 | 2018-08-07 | Globalfoundries Inc. | Method to reduce FinFET short channel gate height |
US10825914B2 (en) * | 2017-11-13 | 2020-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Manufacturing method of semiconductor device |
CN108766878B (zh) * | 2018-05-21 | 2021-01-29 | 上海华力集成电路制造有限公司 | 金属栅极的制造方法 |
US11728171B2 (en) * | 2020-06-25 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with metal gate fill structure |
KR20220145195A (ko) * | 2021-04-21 | 2022-10-28 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
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US20130181265A1 (en) | 2012-01-18 | 2013-07-18 | Globalfoundries Inc. | Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer |
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US20130164930A1 (en) * | 2011-12-22 | 2013-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate height loss improvement for a transistor |
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