JP2018207110A - 二重金属電力レールを有する集積回路の製造方法 - Google Patents

二重金属電力レールを有する集積回路の製造方法 Download PDF

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JP2018207110A
JP2018207110A JP2018108626A JP2018108626A JP2018207110A JP 2018207110 A JP2018207110 A JP 2018207110A JP 2018108626 A JP2018108626 A JP 2018108626A JP 2018108626 A JP2018108626 A JP 2018108626A JP 2018207110 A JP2018207110 A JP 2018207110A
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metal
feature
concave
isolated
nested
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JP2018207110A5 (enExample
Inventor
ドゥ チェ ス
Soo Doo Chae
ドゥ チェ ス
前川　薫
Kaoru Maekawa
薫 前川
スミス ジェフリー
Geoffrey Smith
スミス ジェフリー
ジョイ ニコラス
Joy Nicholas
ジョイ ニコラス
ジェイ．ルーシンク ゲリット
J Leusink Gerrit
ジェイ．ルーシンク ゲリット
ユ カイ−フン
Kai-Hung Yu
ユ カイ−フン
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Publication of JP2018207110A publication Critical patent/JP2018207110A/ja
Publication of JP2018207110A5 publication Critical patent/JP2018207110A5/ja
Priority to JP2023025336A priority Critical patent/JP7492618B2/ja
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H10P14/40—
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01044—Ruthenium [Ru]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2018108626A 2017-06-06 2018-06-06 二重金属電力レールを有する集積回路の製造方法 Pending JP2018207110A (ja)

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US10879115B2 (en) * 2017-11-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
US11121075B2 (en) * 2018-03-23 2021-09-14 Qualcomm Incorporated Hybrid metallization interconnects for power distribution and signaling
US11101175B2 (en) * 2018-11-21 2021-08-24 International Business Machines Corporation Tall trenches for via chamferless and self forming barrier
US11024537B2 (en) * 2019-08-09 2021-06-01 Applied Materials, Inc. Methods and apparatus for hybrid feature metallization
KR102833584B1 (ko) * 2019-09-03 2025-07-15 삼성전자주식회사 반도체 소자
US11450562B2 (en) * 2019-09-16 2022-09-20 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11908738B2 (en) 2021-10-18 2024-02-20 International Business Machines Corporation Interconnect including integrally formed capacitor

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US20170133317A1 (en) * 2015-11-05 2017-05-11 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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JP2002353161A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
KR100447977B1 (ko) * 2002-03-13 2004-09-10 주식회사 하이닉스반도체 듀얼 다마신 공정을 이용한 반도체 소자의 금속 배선 형성방법
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JP2004063995A (ja) * 2002-07-31 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
JP2014187208A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 半導体装置及びその製造方法
US20160005691A1 (en) * 2014-07-02 2016-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid Copper Structure for Advance Interconnect Usage
US20170133317A1 (en) * 2015-11-05 2017-05-11 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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KR102694691B1 (ko) 2024-08-12
JP2023062148A (ja) 2023-05-02
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KR20180133341A (ko) 2018-12-14
US20180350665A1 (en) 2018-12-06

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