JP2018113414A - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

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Publication number
JP2018113414A
JP2018113414A JP2017004445A JP2017004445A JP2018113414A JP 2018113414 A JP2018113414 A JP 2018113414A JP 2017004445 A JP2017004445 A JP 2017004445A JP 2017004445 A JP2017004445 A JP 2017004445A JP 2018113414 A JP2018113414 A JP 2018113414A
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Japan
Prior art keywords
circuit board
resin layer
resin
semiconductor device
semiconductor element
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Pending
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JP2017004445A
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English (en)
Japanese (ja)
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JP2018113414A5 (https=
Inventor
光浩 相澤
Mitsuhiro Aizawa
光浩 相澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017004445A priority Critical patent/JP2018113414A/ja
Priority to US15/866,725 priority patent/US20180204807A1/en
Publication of JP2018113414A publication Critical patent/JP2018113414A/ja
Publication of JP2018113414A5 publication Critical patent/JP2018113414A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2017004445A 2017-01-13 2017-01-13 半導体装置とその製造方法 Pending JP2018113414A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017004445A JP2018113414A (ja) 2017-01-13 2017-01-13 半導体装置とその製造方法
US15/866,725 US20180204807A1 (en) 2017-01-13 2018-01-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017004445A JP2018113414A (ja) 2017-01-13 2017-01-13 半導体装置とその製造方法

Publications (2)

Publication Number Publication Date
JP2018113414A true JP2018113414A (ja) 2018-07-19
JP2018113414A5 JP2018113414A5 (https=) 2019-10-10

Family

ID=62841024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017004445A Pending JP2018113414A (ja) 2017-01-13 2017-01-13 半導体装置とその製造方法

Country Status (2)

Country Link
US (1) US20180204807A1 (https=)
JP (1) JP2018113414A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690198A (zh) * 2020-05-19 2021-11-23 松下知识产权经营株式会社 半导体装置以及半导体装置的制造方法
JP2023177581A (ja) * 2022-06-02 2023-12-14 株式会社村田製作所 積層型半導体パッケージおよびその製造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US12424531B2 (en) * 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11387176B2 (en) * 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
EP4439648A3 (en) 2018-12-18 2025-01-15 MediaTek Inc. Semiconductor package structure
JP7069082B2 (ja) * 2019-05-08 2022-05-17 三菱電機株式会社 電力用半導体装置およびその製造方法
US11570903B2 (en) * 2019-10-16 2023-01-31 Advanced Micro Devices, Inc. Process for conformal coating of multi-row surface-mount components in a lidless BGA package and product made thereby
KR102916276B1 (ko) * 2020-09-02 2026-01-22 에스케이하이닉스 주식회사 3차원 구조의 반도체 장치
US11538760B2 (en) 2020-12-17 2022-12-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
CN113035846B (zh) * 2021-02-03 2026-01-23 日月光半导体制造股份有限公司 封装结构及其形成方法
US11694941B2 (en) * 2021-05-12 2023-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die package with multi-lid structures and method for forming the same
US12394698B2 (en) * 2021-07-23 2025-08-19 Taiwan Semiconductor Manufacturing Company Limited Underfill cushion films for packaging substrates and methods of forming the same
KR20240026636A (ko) * 2022-08-22 2024-02-29 삼성전자주식회사 반도체 패키지

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11260960A (ja) * 1998-03-11 1999-09-24 Sony Corp 半導体パッケージおよびその製造方法
JP2005039206A (ja) * 2003-07-18 2005-02-10 Samsung Electronics Co Ltd 半導体チップ表面実装方法
JP2005252286A (ja) * 2005-04-01 2005-09-15 Hitachi Ltd 自動車用制御コントロールユニットおよびその製造方法並びにｉｃチップパッケージ
JP2007173862A (ja) * 2003-06-24 2007-07-05 Ngk Spark Plug Co Ltd 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体
JP2009027109A (ja) * 2007-07-24 2009-02-05 Taiyo Yuden Co Ltd 電子部品の実装方法及び回路基板
JP2011146519A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
JP2013106031A (ja) * 2011-11-16 2013-05-30 Samsung Electro-Mechanics Co Ltd 半導体パッケージ及びその製造方法
US8986806B1 (en) * 2012-04-20 2015-03-24 Amkor Technology, Inc. Warpage control stiffener ring package and fabrication method

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060051889A1 (en) * 2004-09-08 2006-03-09 Vinu Yamunan Chip assembly reinforcement
JP5211493B2 (ja) * 2007-01-30 2013-06-12 富士通セミコンダクター株式会社 配線基板及び半導体装置
TW200950014A (en) * 2008-05-23 2009-12-01 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
JP5250524B2 (ja) * 2009-10-14 2013-07-31 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8143110B2 (en) * 2009-12-23 2012-03-27 Intel Corporation Methods and apparatuses to stiffen integrated circuit package
KR101678539B1 (ko) * 2010-07-21 2016-11-23 삼성전자 주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
US8580683B2 (en) * 2011-09-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molding die on wafer interposers
US9287194B2 (en) * 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
PT3058566T (pt) * 2013-10-18 2018-03-01 Fraunhofer Ges Forschung Codificação de coeficientes espectrais de um espectro de um sinal de áudio
US9627329B1 (en) * 2014-02-07 2017-04-18 Xilinx, Inc. Interposer with edge reinforcement and method for manufacturing same
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9379032B2 (en) * 2014-09-15 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging having warpage control and methods of forming same
TWI641087B (zh) * 2015-12-28 2018-11-11 Siliconware Precision Industries Co., Ltd. 電子封裝件及封裝用之基板
JP6524003B2 (ja) * 2016-03-17 2019-06-05 東芝メモリ株式会社 半導体装置
US9899305B1 (en) * 2017-04-28 2018-02-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11260960A (ja) * 1998-03-11 1999-09-24 Sony Corp 半導体パッケージおよびその製造方法
JP2007173862A (ja) * 2003-06-24 2007-07-05 Ngk Spark Plug Co Ltd 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体
JP2005039206A (ja) * 2003-07-18 2005-02-10 Samsung Electronics Co Ltd 半導体チップ表面実装方法
JP2005252286A (ja) * 2005-04-01 2005-09-15 Hitachi Ltd 自動車用制御コントロールユニットおよびその製造方法並びにｉｃチップパッケージ
JP2009027109A (ja) * 2007-07-24 2009-02-05 Taiyo Yuden Co Ltd 電子部品の実装方法及び回路基板
JP2011146519A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
JP2013106031A (ja) * 2011-11-16 2013-05-30 Samsung Electro-Mechanics Co Ltd 半導体パッケージ及びその製造方法
US8986806B1 (en) * 2012-04-20 2015-03-24 Amkor Technology, Inc. Warpage control stiffener ring package and fabrication method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690198A (zh) * 2020-05-19 2021-11-23 松下知识产权经营株式会社 半导体装置以及半导体装置的制造方法
JP2023177581A (ja) * 2022-06-02 2023-12-14 株式会社村田製作所 積層型半導体パッケージおよびその製造方法
JP7655276B2 (ja) 2022-06-02 2025-04-02 株式会社村田製作所 積層型半導体パッケージおよびその製造方法

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