JP2018101706A - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】トレンチゲート構造の縦型MOSFETは、エピタキシャル成長させたn-型ドリフト層2およびp+型ベース層6を備える。縦型MOSFETは、n-型ドリフト層2およびp+型ベース層6を貫通するトレンチ18を備え、トレンチ18は、内部に、低濃度薄膜14が設けられている。低濃度薄膜14は、p+型ベース層6と接し、p+型ベース層6と同じ導電型であり、p+型ベース層6より不純物濃度が低い。
【選択図】図1
Description
本発明にかかる半導体装置は、シリコンよりもバンドギャップが広い半導体(以下、ワイドバンドギャップ半導体とする)を用いて構成される。ここでは、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた半導体装置(炭化珪素半導体装置)の構造を例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構造を示す断面図である。図1には、2つの単位セル(素子の機能単位)のみを示し、これらに隣接する他の単位セルを図示省略する。図1に示す実施の形態1にかかる炭化珪素半導体装置は、炭化珪素からなる半導体基体(炭化珪素基体:半導体チップ)100のおもて面(p+型ベース層6側の面)側にMOSゲートを備えたMOSFETである。
次に、実施の形態2にかかる炭化珪素半導体装置の構造について説明する。図9は、実施の形態2にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態2にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、図9に示すように、実施の形態2では、低濃度薄膜14がトレンチ18の底に設けられていない点である。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図16は、実施の形態3にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態3にかかる炭化珪素半導体装置が実施の形態2にかかる炭化珪素半導体装置と異なる点は、図16に示すように、実施の形態3では、トレンチ18の底に接する第1p++型領域3を備えていない点である。
本実施例では、エピタキシャル成長装置内に、炭化珪素基体100を搬入し、炭化珪素基体100の温度を1630℃にして、炭化珪素基体100の表面に、H2ガスをキャリアガスに用いて、原料ガスであるSiH4ガスとC3H8ガスとを同時に供給すると共に、N2を含むドーパントガスを供給して、ガスの圧力を10000Paの圧力に制御して、n型の低濃度薄膜14”を形成した。H2ガスの流量は、100slmとし、SiH4ガスの流量は、50sccmとし、C3H8ガスの流量は、20sccmとし、N2ガスの流量は、3sccmとした。
2 n-型ドリフト層
3 第1p++型領域
4 第2p++型領域
4a 下側第2p++型領域
4b 上側第2p++型領域
5 n型領域
5a 下側n型領域
5b 上側n型領域
6 p+型ベース層
7 n++型ソース領域
8 p+++型コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
12 ソース電極
13 ドレイン電極
14 低濃度薄膜
15 ニッケルシリサイド膜
18 トレンチ
Claims (8)
- 炭化珪素基板のおもて面に設けられた第1導電型の第1半導体層と、
前記第1半導体層の、前記炭化珪素基板側に対して反対側に設けられた第2導電型の第2半導体層と、
前記第2半導体層の内部に選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第2導電型の第1半導体領域と、
前記第1半導体領域および前記第2半導体層を貫通して前記第1半導体層に達するトレンチと、
前記トレンチの内部に設けられた、前記第2半導体層および前記第1半導体層と接する半導体膜と、
前記トレンチの内部、前記半導体膜の内側にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体領域および前記第2半導体層に接する第1電極と、
前記炭化珪素基板の裏面に設けられた第2電極と、
を備え、
前記半導体膜は、前記第2半導体層と接する領域が、前記第2半導体層より不純物濃度の低い第2導電型の領域であることを特徴とする炭化珪素半導体装置。 - 前記半導体膜は、前記第2半導体層と接する領域が、前記第2半導体層より不純物濃度の低い第2導電型であり、前記トレンチの底には設けられていないことを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記半導体膜は、前記トレンチの中心に近づくほど不純物濃度が低くなるプロファイルを有することを特徴とする請求項1または2に記載の炭化珪素半導体装置。
- 炭化珪素基板のおもて面に第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記炭化珪素基板側に対して反対側に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の内部に、前記第2半導体層よりも不純物濃度の高い第2導電型の第1半導体領域を選択的に形成する第3工程と、
前記第1半導体領域および前記第2半導体層を貫通して前記第1半導体層に達するトレンチを形成する第4工程と、
前記トレンチの内部に、前記第2半導体層および前記第1半導体層と接する半導体膜を形成する第5工程と、
前記トレンチの内部、前記半導体膜の内側にゲート絶縁膜を介して設けられたゲート電極を形成する第6工程と、
前記第1半導体領域および前記第2半導体層に接する第1電極を形成する第7工程と、
前記炭化珪素基板の裏面に第2電極を形成する第8工程と、
を備え、
前記第5工程は、前記半導体膜の前記第2半導体層と接する領域を、前記第2半導体層より不純物濃度の低い第2導電型の領域に形成することを特徴とする炭化珪素半導体装置の製造方法。 - 前記第5工程は、
前記第1半導体領域上、前記第2半導体層上、および前記トレンチの内部に、前記半導体膜をエピタキシャル成長させる工程と、
前記トレンチの底の前記半導体膜を除去する工程と、
前記半導体膜の前記第2半導体層と接する領域を、前記第2半導体層より不純物濃度の低い前記第2導電型の領域にする工程と、
を含む工程であることを特徴とする請求項4に記載の炭化珪素半導体装置の製造方法。 - 前記トレンチの底の前記半導体膜を除去する工程は、前記第1半導体領域上、前記第2半導体層上および前記トレンチの側壁の前記半導体膜を薄くし、前記トレンチの底の前記半導体膜を除去することを特徴とする請求項5に記載の炭化珪素半導体装置の製造方法。
- 前記第5工程においては、前記第3工程で形成された前記第1半導体領域を活性化する処理により、前記トレンチの中心に近づくほど不純物濃度が低くなるプロファイルを有する前記半導体膜を形成することを特徴とする請求項4〜6のいずれか一つに記載の炭化珪素半導体装置の製造方法。
- 前記第5工程においては、前記第4工程で形成された前記トレンチに対するアニール処理により、前記トレンチの中心に近づくほど不純物濃度が低くなるプロファイルを有する前記半導体膜を形成することを特徴とする請求項4〜6のいずれか一つに記載の炭化珪素半導体装置の製造方法。
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