JP6335089B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6335089B2 JP6335089B2 JP2014205070A JP2014205070A JP6335089B2 JP 6335089 B2 JP6335089 B2 JP 6335089B2 JP 2014205070 A JP2014205070 A JP 2014205070A JP 2014205070 A JP2014205070 A JP 2014205070A JP 6335089 B2 JP6335089 B2 JP 6335089B2
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- 239000004065 semiconductor Substances 0.000 title claims description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000012535 impurity Substances 0.000 claims description 107
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 71
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 39
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- 239000011229 interlayer Substances 0.000 description 12
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- 229910052757 nitrogen Inorganic materials 0.000 description 2
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Description
まず、本実施の形態によるトレンチ型MOSゲート構造を備える炭化珪素半導体装置の構成およびその製造方法がより明確となると思われるため、本発明者らによって見出されたトレンチ型MOSゲート構造を備える炭化珪素半導体装置における解決しようとする課題について、図13を用いて以下に説明する。図13は、本発明者らが検討したトレンチ型MOSゲート構造を備える炭化珪素半導体装置の要部断面図である。
≪炭化珪素半導体装置≫
本実施の形態による炭化珪素半導体装置の構成を、図1を用いて説明する。ここでは、トレンチ型MOSゲート構造を備える炭化珪素半導体装置であるトレンチゲート型MOSFET(Metal Oxide Semiconductor Field Effect Transistor)の構成について説明する。図1は、トレンチ型MOSゲート構造を備える炭化珪素半導体装置(トレンチゲート型MOSFET)の要部断面図である。
次に、本実施の形態による炭化珪素半導体装置の製造方法を、図2〜図12を用いて工程順に説明する。ここでは、トレンチ型MOSゲート構造を備える炭化珪素半導体装置であるトレンチゲート型MOSFETの製造方法について説明する。図2〜図12は、トレンチ型MOSゲート構造を備える炭化珪素半導体装置(トレンチゲート型MOSFET)の要部断面図である。
まず、図2に示すように、n型の導電性を示す炭化珪素(SiC)からなる基板SBと、この基板SBの主面上にエピタキシャル成長法によって形成されたn型の導電性を示す炭化珪素(SiC)からなるn−型層NEとから構成されるウエハを用意する。基板SBは、ドレイン層として機能する。基板SBの厚さは、例えば350μm程度であり、その不純物濃度は、例えば1×1018cm−3以上である。また、n−型層NEの厚さは、例えば10〜13μm程度であり、その不純物濃度は、例えば8×1015cm−3程度である。
次に、図4に示すように、n型層NIの上面側のn−型層NEに、p型不純物、例えばアルミニウム(Al)をイオン注入法により導入して、p−型ボディー層PBを形成する。p−型ボディー層PBは、例えばn−型層NEの上面(n型層NIと接する面と反対側の面)から深さ方向に0.3μm(0.3μmを含んでもよい)の位置から、n−型層NEとn型層NIとの界面にわたって形成される。すなわち、n−型層NEの上面から0.3μmまでの範囲内には、p−型ボディー層PBは形成されず、また、n型層NIを超えて、n−型ドリフト層NEaには、p−型ボディー層PBは形成されない。
次に、図5に示すように、n−型層NEに、n型不純物、例えば窒素(N)をイオン注入法により導入して、n+型ソース層NSを形成する。n+型ソース層NSは、例えばn−型層NEの上面から、深さ方向に0.3μm(0.3μmを含んでもよい)の位置にわたって形成される。
次に、図6に示すように、n+型ソース層NSの上面(p−型ボディー層PBと接する面と反対側の面)上に、リソグラフィ技術によりレジストパターンRP1を形成する。そして、レジストパターンRP1をマスクとしてn+型ソース層NSに、p型不純物、例えばアルミニウム(Al)をイオン注入法により導入して、所望する領域に、p−型ボディー層PBに達するp+型コンタクト層PCを形成する。具体的には、p+型コンタクト層PCは、例えばn+型ソース層NSの上面から、深さ方向に0.5μm(0.5μmを含んでもよい)の位置にわたって形成される。p+型コンタクト層PCの不純物濃度は、n+型ソース層NSの不純物濃度よりも2桁程度高い、例えば1×1021cm−3以上である。
次に、図7に示すように、n+型ソース層NSおよびp+型コンタクト層PCの上面上に、酸化膜SOMを、例えばCVD法により形成する。酸化膜SOMは、例えばTEOS(Tetra Ethyl Ortho Silicate;Si(OC2H5)4)膜であり、その厚さは、例えば0.5〜1μm程度である。
次に、図9に示すように、酸化膜SOMの開口部から、トレンチTRの側面に露出するp−型ボディー層PBに対してp型不純物、例えばアルミニウム(Al)を斜めイオン注入することによりp型チャネル層CHを形成する。一般に、トレンチTRは平面視において矩形の形状であるので、ウエハを90℃ずつ回転させることにより、4回方向を変えて斜めイオン注入を行い、平面視において矩形形状の4辺のそれぞれに対してp型チャネル層CHを形成する。
本実施の形態では、酸化膜SOMの厚さdは、例えば0.5〜1μm程度、トレンチTRの深さcは、例えば1.0〜1.2μm程度であることから、イオン注入角θは、3〜15°と決定することができる。
次に、図10に示すように、ハードマスクHMをウエットエッチング法により除去した後、熱酸化法およびCVD法によりトレンチTRの内壁(側面および底面)、並びにn+型ソース層NSおよびp+型コンタクト層PCの上面に酸化膜SOGを形成し、続いて、酸化膜SOG上にトレンチTRの内部を埋め込むように、例えばn型不純物を含む多結晶シリコン膜PSを堆積する。酸化膜SOGの厚さは、例えば30〜100nm程度であり、多結晶シリコン膜PSの不純物濃度は、例えば1×1020cm−3程度である。
次に、図11に示すように、レジストパターンRP3を除去した後、第1ゲート電極GE1およびゲート絶縁膜GIを覆うように、第1ゲート電極GE1、n+型ソース層NSおよびp+型コンタクト層PCの上面にCVD法により層間絶縁膜ILを形成する。
CT1,CT2 接続孔
DE ドレイン電極
GE1 第1ゲート電極
GE2 第2ゲート電極
GI ゲート絶縁膜
HM ハードマスク
IL 層間絶縁膜
NE n−型層(第3の層)
NEa n−型ドリフト層
NI n型層(第1の層)
NS n+型ソース層
PB p−型ボディー層
PC p+型コンタクト層
PI p型層(第2の層)
PR p型層
PS 多結晶シリコン膜
RP1,RP2,RP3 レジストパターン
SB 基板
SE ソース電極
SL シリサイド層
SOG 酸化膜
SOM 酸化膜
TR トレンチ
Claims (8)
- (a)炭化珪素からなる第1導電型の基板の主面上に、前記第1導電型のドリフト層、前記第1導電型の第1の層、前記第1導電型と異なる第2導電型のボディー層および前記第1導電型のソース層が順次積層された構造を形成する工程、
(b)前記ソース層上に、所定の領域に開口部を有するマスクを形成する工程、
(c)前記マスクを用いて、前記ソース層、前記ボディー層および前記第1の層を加工して、前記ソース層、前記ボディー層および前記第1の層を貫通し、前記ドリフト層に達するトレンチを形成する工程、
(d)前記基板の主面の法線方向に対して第1角度を有する方向から、前記第2導電型の不純物をイオン注入して、前記トレンチの側面に露出する前記ボディー層に、前記トレンチの側面に沿って前記第2導電型のチャネル層を形成し、前記トレンチの底面に露出する前記ドリフト層に、前記トレンチの底面に沿って前記第2導電型の第2の層を形成する工程、
(e)前記トレンチの前記側面および前記底面を覆うようにゲート絶縁膜を形成する工程、
(f)前記トレンチの内部に前記ゲート絶縁膜を介してゲート電極を形成する工程、
を含む、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程における前記第1角度は、3〜15度である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、
(a1)前記基板の主面上に、炭化珪素からなる前記第1導電型の第3の層を形成する工程、
(a2)前記第3の層の上面から第1距離を有する前記第3の層内の第1位置と、前記第3の層の上面から前記第1距離よりも大きい第2距離を有する前記第3の層内の第2位置との間に、前記第1導電型の不純物をイオン注入して、前記第1の層を形成する工程、
(a3)前記第1位置と、前記第3の層の上面から前記第1距離よりも小さい第3距離を有する前記第3の層内の第3位置との間に、前記第2導電型の不純物をイオン注入して、前記ボディー層を形成する工程、
(a4)前記第3の層の上面と、前記第3位置との間に、前記第1導電型の不純物をイオン注入して、前記ソース層を形成する工程、
を含み、
前記(a3)工程では、注入エネルギーが互いに異なる2回以上のイオン注入を行う、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1の層の不純物濃度が前記ドリフト層の不純物濃度および前記チャネル層の不純物濃度よりも高く、前記チャネル層の不純物濃度が前記ボディー層の不純物濃度よりも高い、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記チャネル層の不純物濃度は、前記ボディー層の不純物濃度よりも10倍以上高い、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記チャネル層の不純物濃度は、前記トレンチの側面に沿って均一である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記チャネル層の不純物濃度と、前記第2の層の不純物濃度とが同じである、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記チャネル層と前記第2の層との間に、前記第1の層が形成されている、半導体装置の製造方法。
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JP6115678B1 (ja) | 2016-02-01 | 2017-04-19 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
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JP7017733B2 (ja) * | 2017-09-07 | 2022-02-09 | 国立研究開発法人産業技術総合研究所 | 半導体装置および半導体装置の製造方法 |
JP7135302B2 (ja) * | 2017-11-08 | 2022-09-13 | 富士電機株式会社 | 炭化シリコン半導体装置及びその製造方法 |
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