JP2018085487A - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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Publication number
JP2018085487A
JP2018085487A JP2016229239A JP2016229239A JP2018085487A JP 2018085487 A JP2018085487 A JP 2018085487A JP 2016229239 A JP2016229239 A JP 2016229239A JP 2016229239 A JP2016229239 A JP 2016229239A JP 2018085487 A JP2018085487 A JP 2018085487A
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Japan
Prior art keywords
semiconductor device
electrode layer
resin
manufacturing
semiconductor
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Pending
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JP2016229239A
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English (en)
Japanese (ja)
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JP2018085487A5 (enrdf_load_stackoverflow
Inventor
佑也 五郎丸
Yuya Goromaru
佑也 五郎丸
木村　浩
Hiroshi Kimura
浩 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Torex Semiconductor Ltd
Maxell Ltd
Original Assignee
Maxell Holdings Ltd
Torex Semiconductor Ltd
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Publication date
Application filed by Maxell Holdings Ltd, Torex Semiconductor Ltd filed Critical Maxell Holdings Ltd
Priority to JP2016229239A priority Critical patent/JP2018085487A/ja
Publication of JP2018085487A publication Critical patent/JP2018085487A/ja
Publication of JP2018085487A5 publication Critical patent/JP2018085487A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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JP2016229239A 2016-11-25 2016-11-25 半導体装置の製造方法および半導体装置 Pending JP2018085487A (ja)

Priority Applications (1)

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JP2016229239A JP2018085487A (ja) 2016-11-25 2016-11-25 半導体装置の製造方法および半導体装置

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JP2016229239A JP2018085487A (ja) 2016-11-25 2016-11-25 半導体装置の製造方法および半導体装置

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JP2018085487A true JP2018085487A (ja) 2018-05-31
JP2018085487A5 JP2018085487A5 (enrdf_load_stackoverflow) 2019-11-28

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020027850A (ja) * 2018-08-10 2020-02-20 ローム株式会社 半導体装置および半導体装置の製造方法
JP2023045460A (ja) * 2021-09-22 2023-04-03 ローム株式会社 半導体装置および半導体装置の製造方法
WO2023112677A1 (ja) * 2021-12-13 2023-06-22 ローム株式会社 半導体装置および半導体装置の製造方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098205A (ja) * 1995-06-14 1997-01-10 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2002009196A (ja) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd 半導体装置の製造方法
JP2002289739A (ja) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法
JP2009200175A (ja) * 2008-02-20 2009-09-03 Mitsumi Electric Co Ltd 半導体装置及びその製造方法
EP2361000A1 (en) * 2010-02-11 2011-08-24 Nxp B.V. Leadless chip package mounting method and carrier
JP2011205153A (ja) * 2011-07-20 2011-10-13 Dainippon Printing Co Ltd 樹脂封止型半導体装置および半導体装置用回路部材
JP2013235999A (ja) * 2012-05-10 2013-11-21 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2015073120A (ja) * 2009-09-29 2015-04-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2015145651A1 (ja) * 2014-03-27 2015-10-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP2016127261A (ja) * 2014-12-27 2016-07-11 日立マクセル株式会社 半導体装置用基板、半導体装置用基板の製造方法、及び半導体装置
JP2017175131A (ja) * 2016-03-17 2017-09-28 ローム株式会社 半導体装置およびその製造方法
JP2017228559A (ja) * 2016-06-20 2017-12-28 ローム株式会社 半導体装置およびその製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098205A (ja) * 1995-06-14 1997-01-10 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2002009196A (ja) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd 半導体装置の製造方法
JP2002289739A (ja) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法
JP2009200175A (ja) * 2008-02-20 2009-09-03 Mitsumi Electric Co Ltd 半導体装置及びその製造方法
JP2015073120A (ja) * 2009-09-29 2015-04-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP2361000A1 (en) * 2010-02-11 2011-08-24 Nxp B.V. Leadless chip package mounting method and carrier
JP2011205153A (ja) * 2011-07-20 2011-10-13 Dainippon Printing Co Ltd 樹脂封止型半導体装置および半導体装置用回路部材
JP2013235999A (ja) * 2012-05-10 2013-11-21 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
WO2015145651A1 (ja) * 2014-03-27 2015-10-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP2016127261A (ja) * 2014-12-27 2016-07-11 日立マクセル株式会社 半導体装置用基板、半導体装置用基板の製造方法、及び半導体装置
JP2017175131A (ja) * 2016-03-17 2017-09-28 ローム株式会社 半導体装置およびその製造方法
JP2017228559A (ja) * 2016-06-20 2017-12-28 ローム株式会社 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020027850A (ja) * 2018-08-10 2020-02-20 ローム株式会社 半導体装置および半導体装置の製造方法
JP7179526B2 (ja) 2018-08-10 2022-11-29 ローム株式会社 半導体装置および半導体装置の製造方法
JP2023045460A (ja) * 2021-09-22 2023-04-03 ローム株式会社 半導体装置および半導体装置の製造方法
WO2023112677A1 (ja) * 2021-12-13 2023-06-22 ローム株式会社 半導体装置および半導体装置の製造方法

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