JP2018064124A - 半導体集積回路装置 - Google Patents
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Abstract
Description
図1は第1の実施形態に係る半導体集積回路装置が備えたスタンダードセルのレイアウト構成例を示す平面図である。また、図2は図1の構成の線K1−K1における断面図であり、図3は図1の構成の線K2−K2における断面図である。なお、本実施形態では説明を簡単にするために、インバータセルを例として示しているが、これに限られるものではない。
図6は第2の実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。なお、本実施形態では説明を簡単にするために、インバータセルを例として示しているが、これに限られるものではない。また、隣接するスタンダードセル2A,2Bは互いに異なる種類のセルであってもかまわない。
図10は第3の実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。図10では、図面横方向(第1方向に相当)に並べて配置されたスタンダードセル3A,3B,3C,3Dを含む第1セル列CR1と、図面横方向に並べて配置されたスタンダードセル3E,3F,3G,3Hを含み、図面縦方向(第1方向と垂直をなす第2方向に相当)において第1セル列CR1に隣接して配置された第2セル列CR2とを示している。なお、図10では説明の簡単のために、セル枠と、第1および第2セル列CR1,CR2の間のセル列境界CRBに沿って並んだフィン以外は、図示を省略している。第1セル列CR1では、セル列境界CRBに沿って、図面横方向に延びるフィン31,32,33a,33b,34が同一直線上に並んでいる。第2セル列CR2では、セル列境界CRBに沿って、図面横方向に延びるフィン35a,35b,36,37,38a,38bが同一直線上に並んでいる。
2A,2B スタンダードセル
3A,3B,3C,3D,3E,3F,3G,3H スタンダードセル
5f ローカル配線
6f コンタクト
8c メタル配線
11,12 アクティブフィン
13,14 ダミーフィン
15,15A ゲート配線
16,17 ダミーフィンに設けられたゲート配線
21,22,23,24 アクティブフィン
25 ダミーフィン
26,27 ゲート配線
28 ダミーフィンに設けられたゲート配線
29 拡散層配線
31,33a アクティブフィン
32,33b ダミーフィン
CB セル境界
CR1 第1セル列
CR2 第2セル列
CRB セル列境界
Claims (16)
- フィン型トランジスタを備えた第1スタンダードセルを備え、
前記第1スタンダードセルは、第1方向に延びており、かつ、前記第1方向と垂直をなす第2方向において並べて配置された複数のフィンを備え、
前記複数のフィンは、
アクティブトランジスタを構成するアクティブフィンと、
前記第2方向において、前記アクティブフィンと前記第1スタンダードセルの端との間に、配置されたダミーフィンとを含む
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記ダミーフィンは、前記第1スタンダードセルにおけるフィンの中で、前記端に最も近い位置に配置されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記アクティブフィンおよび前記ダミーフィンは、同一導電型領域に配置されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記ダミーフィンは、ゲート配線が設けられており、非アクティブトランジスタを構成するフィンである
ことを特徴とする半導体集積回路装置。 - 請求項4記載の半導体集積回路装置において、
前記ダミーフィンに設けられたゲート配線は、前記アクティブフィンに設けられたゲート配線と、前記第2方向に延びる同一直線上に、一体に形成されている
ことを特徴とする半導体集積回路装置。 - 請求項4記載の半導体集積回路装置において、
前記ダミーフィンに設けられたゲート配線は、前記アクティブフィンに設けられたゲート配線と、前記第2方向に延びる同一直線上に位置し、かつ、分離されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記ダミーフィンは、ゲート配線が設けられておらず、トランジスタを構成しないフィンである
ことを特徴とする半導体集積回路装置。 - フィン型トランジスタを備えた第1および第2スタンダードセルを備え、
前記第1および第2スタンダードセルは、それぞれ、第1方向に延びており、かつ、前記第1方向と垂直をなす第2方向において並べて配置された複数のフィンを備え、
前記第1および第2スタンダードセルは、前記第2方向において隣接して配置されており、前記第1スタンダードセルと前記第2スタンダードセルとの間のセル境界において、ダミーフィンが配置されている
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記ダミーフィンは、ゲート配線が設けられておらず、トランジスタを構成しないフィンである
ことを特徴とする半導体集積回路装置。 - 請求項9記載の半導体集積回路装置において、
前記ダミーフィンの上方に、前記第1方向に延びるメタル配線が設けられており、
前記ダミーフィンは、ローカル配線およびコンタクトを介して、前記メタル配線に接続されている
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記ダミーフィンは、前記第1および第2スタンダードセルの少なくともいずれか一方において、拡散層配線を介して、アクティブトランジスタを構成するアクティブフィンと接続されている
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記ダミーフィンは、ゲート配線が設けられており、非アクティブトランジスタを構成するフィンである
ことを特徴とする半導体集積回路装置。 - 第1方向に並べて配置されたスタンダードセルからなる第1セル列と、
前記第1方向に並べて配置されたスタンダードセルからなり、前記第1方向と垂直をなす第2方向において前記第1セル列に隣接して配置された第2セル列とを備え、
前記第1セル列は、
フィン型アクティブトランジスタを備え、前記第1方向に延びるフィンを備えた第1スタンダードセルと、
前記第1方向に延びるフィンを備えた第2スタンダードセルとを備え、
前記第2スタンダードセルは、前記第1スタンダードセルにおいて前記第1セル列と前記第2セル列との間のセル列境界に最も近い位置に配置された第1フィンと、前記第2方向における同一位置に、ダミーフィンが配置されている
ことを特徴とする半導体集積回路装置。 - 請求項13記載の半導体集積回路装置において、
前記第1フィンは、前記第1セル列におけるフィンの中で、前記セル列境界に最も近い位置に配置されている
ことを特徴とする半導体集積回路装置。 - 請求項13記載の半導体集積回路装置において、
前記第2スタンダードセルは、TAPセル、アンテナセル、フィラーセル、または、容量セルである
ことを特徴とする半導体集積回路装置。 - 請求項13記載の半導体集積回路装置において、
前記第2スタンダードセルは、前記ダミーフィンと同一直線上に、アクティブトランジスタを構成するアクティブフィンが配置されている
ことを特徴とする半導体集積回路装置。
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WO2015029280A1 (ja) * | 2013-08-28 | 2015-03-05 | パナソニック株式会社 | 半導体集積回路装置 |
JP6396834B2 (ja) * | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9859210B2 (en) * | 2015-06-19 | 2018-01-02 | Qualcomm Incorporated | Integrated circuits having reduced dimensions between components |
KR102318131B1 (ko) * | 2015-12-03 | 2021-10-26 | 삼성전자주식회사 | 반도체 장치 |
US9721841B1 (en) * | 2016-04-27 | 2017-08-01 | United Microelectronics Corp. | Electronic circuit of fin FET and methof for fabricating the electronic circuit |
CN109075126B (zh) * | 2016-05-06 | 2023-01-31 | 株式会社索思未来 | 半导体集成电路装置 |
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JP6875643B2 (ja) | 2016-07-01 | 2021-05-26 | 株式会社ソシオネクスト | 半導体集積回路装置 |
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