JP2017522717A - 高電圧トランジスタ及び低電圧非プレーナ型トランジスタのモノリシック集積 - Google Patents
高電圧トランジスタ及び低電圧非プレーナ型トランジスタのモノリシック集積 Download PDFInfo
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- JP2017522717A JP2017522717A JP2016567070A JP2016567070A JP2017522717A JP 2017522717 A JP2017522717 A JP 2017522717A JP 2016567070 A JP2016567070 A JP 2016567070A JP 2016567070 A JP2016567070 A JP 2016567070A JP 2017522717 A JP2017522717 A JP 2017522717A
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- 230000010354 integration Effects 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 241
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims description 55
- 238000009792 diffusion process Methods 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000000295 complement effect Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 abstract description 15
- 239000002070 nanowire Substances 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 description 43
- 230000008569 process Effects 0.000 description 13
- 238000004891 communication Methods 0.000 description 12
- 230000008859 change Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- -1 but not limited to Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000001364 causal effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
Description
Claims (21)
- 基板の第1の領域の上に配置された高電圧FETを備える集積回路構造(IC構造)であって、前記高電圧FETは、
各々が前記基板のドープウェルから延在し、複数の前記ドープウェルを分離するチャネル領域をその間に有する、ペアの非プレーナ型半導体本体と、
第1の前記非プレーナ型半導体本体におけるソース領域と、
第2の前記非プレーナ型半導体本体におけるドレイン領域と、
チャネル領域の上に配置されたゲートスタックと、
を含む、IC構造。 - 前記基板の第2の領域の上に配置された非プレーナ型FETをさらに備え、前記非プレーナ型FETは、
第3の非プレーナ型半導体本体と、
前記第3の非プレーナ型半導体本体内に配置され、前記第3の非プレーナ型半導体本体内の第2のチャネル領域によって分離される第2のソース領域及び第2のドレイン領域と、
前記第2のチャネル領域の上に配置された第2のゲートスタックと、
を含む、請求項1に記載のIC構造。 - 前記チャネル領域は、前記基板の平坦部分であり、
前記ゲートスタックは、前記チャネル領域の上に配置され、かつ、前記ペアの非プレーナ型半導体本体をさらに囲む分離誘電体をさらに含む、
請求項2に記載のIC構造。 - 前記ゲートスタックは、前記分離誘電体の上に配置されたドープポリシリコン電極を含み、
前記第2のゲートスタックは、等しい酸化物厚さ(EOT)を有する金属電極及びゲート誘電体を含み、前記金属電極及び前記ゲート誘電体のEOTは、前記分離誘電体のEOTより低い、
請求項3に記載のIC構造。 - 複数の前記ドープウェルは、前記チャネル領域のものと相補的な第1の導電型であり、
前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体は、前記第1の導電型にドープされ、かつ、複数の前記ドープウェルのうち第1のドープウェルと電気的に接続され、
前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体は、前記第1の導電型にドープされ、かつ、複数の前記ドープウェルのうち第2のドープウェルと電気的に接続される、
請求項1から4のいずれか1項に記載のIC構造。 - 前記ソース領域は、前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体における大量ドープ領域のペアの一方であり、
前記ドレイン領域は、前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体における大量ドープ領域のペアの一方であり、
前記高電圧FETは、複数の拡散コンタクトをさらに含み、前記複数の拡散コンタクトの1つは、前記大量ドープ領域の各々にランディングする、
請求項1から5のいずれか1項に記載のIC構造。 - 前記高電圧FETは、ダミーゲートスタックのペアをさらに含み、第1のダミーゲートスタックは、第1の前記非プレーナ型半導体本体の上に配置され、第2のダミーゲートスタックは、第2の前記非プレーナ型半導体本体の上に配置される、請求項1から6のいずれか1項に記載のIC構造。
- 前記高電圧FETは、ダミーゲートスタックのペアをさらに含み、第1のダミーゲートスタックは、第1の前記非プレーナ型半導体本体の上に配置され、第2のダミーゲートスタックは、第2の前記非プレーナ型半導体本体の上に配置され、前記ダミーゲートスタックの各々は、短チャネルゲートスタックと実質的に同じ材料を含む、請求項2に記載のIC構造。
- 前記ソース領域は、前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体における大量ドープ領域のペアの一方であり、
前記ドレイン領域は、前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体における大量ドープ領域のペアの一方であり、
短チャネルの前記高電圧FETは、複数の拡散コンタクトをさらに含み、前記複数の拡散コンタクトの1つは、前記大量ドープ領域、前記第2のソース領域、及び前記第2のドレイン領域の各々にランディングする、
請求項2に記載のIC構造。 - 基板の上に配列され、第1の次元に沿って延在する自身の最大長と平行に方向づけられる、複数の非プレーナ型半導体本体と、
前記基板に配置され、ペアの非プレーナ型半導体本体を囲み、かつ、前記第1の次元又は第1の次元に直交する第2の次元のいずれかに沿って互いに整合される、ペアのドープウェルと、
複数の前記ドープウェルの上に配置され、前記複数の非プレーナ型半導体本体を囲む分離誘電体と、
前記ペアのドープウェルの間において前記分離誘電体の上に配置されたゲート電極であって、複数の前記ドープウェルが前記第2の次元において整合される場合に前記第1の次元においてゲート長(ゲート長Lg)を画定し、複数の前記ドープウェルが前記第1の次元において整合される場合に前記第2の次元において前記Lgを画定する、ゲート電極と、
前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体におけるソース領域と、
前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体におけるドレイン領域と、
を備える、集積回路構造(IC構造)。 - 前記ペアのドープウェルの外側における前記基板の領域に配置された、第3の前記非プレーナ型半導体本体と、
前記第3の非プレーナ型半導体本体の上に配置された第2のゲート電極と、
前記第3の非プレーナ型半導体本体における第2のソース及びドレインコンタクトランディングと、
をさらに備える、請求項10に記載のIC構造。 - 前記基板の上に配列された前記複数の非プレーナ型半導体本体の各々は、前記第2の次元に延在する前記基板の第1の幅で離間する複数の半導体本体の群における1つの半導体本体であり、
前記ペアのドープウェルは、少なくとも前記第1の幅の上に延在し、かつ、前記第1の次元において互いに整合され、
前記第2の次元における前記ゲート長Lgは、前記第1の幅と少なくとも等しい、
請求項10又は11に記載のIC構造。 - 前記基板の上に配列された前記複数の非プレーナ型半導体本体の各々は、前記第2の次元に延在する前記基板の第1の幅で離間する複数の半導体本体の群における1つの半導体本体であり、
前記ペアのドープウェルは、少なくとも前記第1の幅の上に延在し、かつ、前記第2の次元において互いに整合され、
前記第2の次元における前記ゲート長Lgは、前記複数の非プレーナ型半導体本体の最大長以下である、
請求項10から12のいずれか1項に記載のIC構造。 - 基板の第1の部分の上に高電圧電界効果トランジスタ(FET)を製造する方法であって、
基板上において自身を囲む分離誘電体の上に延在する複数の非プレーナ型半導体本体を形成する段階と、
ペアの非プレーナ型半導体本体を通して注入することによって、前記基板に別個の複数のドープウェルを形成する段階と、
前記複数のドープウェルの間において前記分離誘電体の上にゲート電極を堆積させる段階と、
前記複数のドープウェルと電気的に連結された前記ペアの非プレーナ型半導体本体に、ソース/ドレイン領域を形成する段階と、
前記ソース/ドレイン領域に複数の拡散コンタクトを形成する段階と、
を備える、方法。 - 前記基板の第2の部分の上の第2の領域に非プレーナ型FETを形成する段階をさらに備え、前記非プレーナ型FETを形成する段階は、
前記複数のドープウェルの外側において、前記複数の非プレーナ型半導体本体のうち1つ又は複数の上にゲートスタックを形成する段階と、
前記複数のドープウェルの外側において、前記1つ又は複数の非プレーナ型半導体本体に第2のソース/ドレイン領域を形成する段階と、
前記第2のソース/ドレイン領域に複数の第2の拡散コンタクトを形成する段階と、
をさらに含む、請求項14に記載の方法。 - 前記複数のドープウェルと同じ導電型の不純物を、前記ゲート電極に隣接する前記分離誘電体を通して前記ゲート電極に注入することによって、前記ゲート電極をドープし、分離された前記複数のドープウェルの先端部を形成する段階をさらに備える、請求項14又は15に記載の方法。
- 前記ソース/ドレイン領域を形成する段階は、前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体にソース/ドレイン領域の第1のペアを形成し、前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体にソース/ドレイン領域の第2のペアを形成する段階をさらに含み、
前記複数の拡散コンタクトを形成する段階は、前記ソース/ドレイン領域の第1のペアに対してソース/ドレインコンタクトの第1のペアを形成し、前記ソース/ドレイン領域の第2のペアに対して複数の拡散コンタクトの第2のペアを形成する段階をさらに含み、
前記方法は、前記複数の拡散コンタクトの第1のペアを電気的に並列に相互接続し、前記複数の拡散コンタクトの第2のペアを電気的に並列に相互接続する段階をさらに備える、
請求項14から16のいずれか1項に記載の方法。 - 前記複数のドープウェルの外側において、前記複数の非プレーナ型半導体本体の1つ又は複数の上にゲートスタックを形成する段階は、前記複数のドープウェルと電気的に連結された前記ペアの非プレーナ型半導体本体の各々の上に、ダミーゲートスタックを形成する段階をさらに含む、請求項15に記載の方法。
- プロセッサ論理回路と、
前記プロセッサ論理回路と連結されたメモリ回路と、
前記プロセッサ論理回路と連結され、無線送信回路及び無線受信回路を含むRF回路と、
DC電源を受信する入力部と、プロセッサ論理回路、メモリ回路、又はRF回路の少なくとも1つと連結された出力部とを含む電力管理回路と、
を備え、
前記RF回路又は電力管理回路の少なくとも1つは、基板の第1の領域の上に配置された高電圧FETを含み、前記高電圧FETは、
各々が前記基板のドープウェルから延在し、複数の前記ドープウェルを分離するチャネル領域をその間に有するペアの非プレーナ型半導体本体と、
第1の前記非プレーナ型半導体本体におけるソース領域と、
第2の前記非プレーナ型半導体本体におけるドレイン領域と、
チャネル領域の上に配置されたゲートスタックと、
をさらに含む、システムオンチップ(SoC)。 - 前記RF回路又は電力管理回路の少なくとも1つは、前記基板の第2の領域の上に配置された非プレーナ型FETを含み、前記非プレーナ型FETは、
第3の非プレーナ型半導体本体と、
前記第3の非プレーナ型半導体本体内に配置され、第2のチャネル領域によって分離された第2のソース領域及び第2のドレイン領域と、
前記第2のチャネル領域の上に配置された第2のゲートスタックと、
をさらに含む、請求項19に記載のSoC。 - 前記ソース領域は、前記ペアの非プレーナ型半導体本体のうち第1の非プレーナ型半導体本体における、大量ドープ領域のペアの一方であり、
前記ドレイン領域は、前記ペアの非プレーナ型半導体本体のうち第2の非プレーナ型半導体本体における大量ドープ領域のペアの一方であり、
短チャネルの前記高電圧FETは、複数の拡散コンタクトをさらに含み、前記複数の拡散コンタクトの1つは、前記大量ドープ領域、第2のソース領域及び第2のドレイン領域の各々にランディングする、
請求項20に記載のSoC。
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Also Published As
Publication number | Publication date |
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CN106463533A (zh) | 2017-02-22 |
JP6533237B2 (ja) | 2019-06-19 |
TW201611287A (zh) | 2016-03-16 |
US20170025533A1 (en) | 2017-01-26 |
EP3158586A4 (en) | 2018-01-17 |
KR102218368B1 (ko) | 2021-02-22 |
EP3158586A1 (en) | 2017-04-26 |
CN106463533B (zh) | 2021-09-28 |
WO2015195134A1 (en) | 2015-12-23 |
KR20170017887A (ko) | 2017-02-15 |
TWI600160B (zh) | 2017-09-21 |
US10312367B2 (en) | 2019-06-04 |
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