JP2017517142A - 低背基板のためのパターン間パターン - Google Patents
低背基板のためのパターン間パターン Download PDFInfo
- Publication number
- JP2017517142A JP2017517142A JP2016562244A JP2016562244A JP2017517142A JP 2017517142 A JP2017517142 A JP 2017517142A JP 2016562244 A JP2016562244 A JP 2016562244A JP 2016562244 A JP2016562244 A JP 2016562244A JP 2017517142 A JP2017517142 A JP 2017517142A
- Authority
- JP
- Japan
- Prior art keywords
- patterned metal
- metal layer
- substrate
- layer
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
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- H10P50/00—
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- H10W20/01—
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- H10W20/031—
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- H10W20/057—
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- H10W20/063—
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- H10W20/081—
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- H10W20/089—
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- H10W20/435—
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- H10W20/48—
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- H10W70/05—
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- H10W70/685—
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- H10W72/252—
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- H10W90/724—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/253,798 | 2014-04-15 | ||
| US14/253,798 US9269610B2 (en) | 2014-04-15 | 2014-04-15 | Pattern between pattern for low profile substrate |
| PCT/US2015/025435 WO2015160671A1 (en) | 2014-04-15 | 2015-04-10 | Pattern between pattern for low profile substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017517142A true JP2017517142A (ja) | 2017-06-22 |
| JP2017517142A5 JP2017517142A5 (enExample) | 2018-05-10 |
Family
ID=53005702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016562244A Pending JP2017517142A (ja) | 2014-04-15 | 2015-04-10 | 低背基板のためのパターン間パターン |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9269610B2 (enExample) |
| EP (1) | EP3132469B1 (enExample) |
| JP (1) | JP2017517142A (enExample) |
| KR (1) | KR20160145572A (enExample) |
| CN (1) | CN106575623A (enExample) |
| BR (1) | BR112016023947A2 (enExample) |
| WO (1) | WO2015160671A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346821A (zh) * | 2018-09-19 | 2019-02-15 | 中国科学院上海微系统与信息技术研究所 | 圆片级硅基集成小型化分形天线及其制备方法 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12044965B2 (en) * | 2020-02-12 | 2024-07-23 | Hutchinson Technology Incorporated | Method for forming components without adding tabs during etching |
| US20220093505A1 (en) * | 2020-09-24 | 2022-03-24 | Intel Corporation | Via connections for staggered interconnect lines |
| US12500162B2 (en) * | 2021-12-22 | 2025-12-16 | Intel Corporation | Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition |
| US20230395506A1 (en) * | 2022-06-06 | 2023-12-07 | Intel Corporation | Self-aligned staggered integrated circuit interconnect features |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005236018A (ja) * | 2004-02-19 | 2005-09-02 | Alps Electric Co Ltd | 微細配線構造および微細配線構造の製造方法 |
| JP2006344664A (ja) * | 2005-06-07 | 2006-12-21 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3114679A1 (de) * | 1980-04-11 | 1982-01-14 | Hitachi, Ltd., Tokyo | Integrierte schaltung mit mehrschichtenverbindungen |
| JPH0750710B2 (ja) | 1990-06-06 | 1995-05-31 | 富士ゼロックス株式会社 | 多層配線構造 |
| KR920017227A (ko) | 1991-02-05 | 1992-09-26 | 김광호 | 반도체장치의 층간콘택 구조 및 그 제조방법 |
| US6414367B1 (en) | 1999-10-28 | 2002-07-02 | National Semiconductor Corporation | Interconnect exhibiting reduced parasitic capacitance variation |
| JP2002299555A (ja) | 2001-03-30 | 2002-10-11 | Seiko Epson Corp | 集積回路およびその製造方法 |
| KR100808557B1 (ko) | 2002-05-16 | 2008-02-29 | 매그나칩 반도체 유한회사 | 엠아이엠 캐패시터 형성방법 |
| JP4559757B2 (ja) | 2004-03-18 | 2010-10-13 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2007194476A (ja) | 2006-01-20 | 2007-08-02 | Shinko Electric Ind Co Ltd | 多層配線基板の製造方法 |
| US20110215465A1 (en) * | 2010-03-03 | 2011-09-08 | Xilinx, Inc. | Multi-chip integrated circuit |
| US8377792B2 (en) * | 2010-04-07 | 2013-02-19 | National Semiconductor Corporation | Method of forming high capacitance semiconductor capacitors with a single lithography step |
| WO2012005524A2 (en) * | 2010-07-08 | 2012-01-12 | Lg Innotek Co., Ltd. | The printed circuit board and the method for manufacturing the same |
| JP2012094662A (ja) | 2010-10-26 | 2012-05-17 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法 |
| US8722505B2 (en) * | 2010-11-02 | 2014-05-13 | National Semiconductor Corporation | Semiconductor capacitor with large area plates and a small footprint that is formed with shadow masks and only two lithography steps |
| US8551856B2 (en) * | 2011-09-22 | 2013-10-08 | Northrop Grumman Systems Corporation | Embedded capacitor and method of fabricating the same |
| US9012966B2 (en) * | 2012-11-21 | 2015-04-21 | Qualcomm Incorporated | Capacitor using middle of line (MOL) conductive layers |
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2014
- 2014-04-15 US US14/253,798 patent/US9269610B2/en active Active
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2015
- 2015-04-10 JP JP2016562244A patent/JP2017517142A/ja active Pending
- 2015-04-10 KR KR1020167028148A patent/KR20160145572A/ko not_active Withdrawn
- 2015-04-10 CN CN201580019675.3A patent/CN106575623A/zh active Pending
- 2015-04-10 WO PCT/US2015/025435 patent/WO2015160671A1/en not_active Ceased
- 2015-04-10 BR BR112016023947A patent/BR112016023947A2/pt not_active IP Right Cessation
- 2015-04-10 EP EP15718725.3A patent/EP3132469B1/en not_active Not-in-force
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005236018A (ja) * | 2004-02-19 | 2005-09-02 | Alps Electric Co Ltd | 微細配線構造および微細配線構造の製造方法 |
| JP2006344664A (ja) * | 2005-06-07 | 2006-12-21 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346821A (zh) * | 2018-09-19 | 2019-02-15 | 中国科学院上海微系统与信息技术研究所 | 圆片级硅基集成小型化分形天线及其制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015160671A9 (en) | 2016-06-09 |
| US9269610B2 (en) | 2016-02-23 |
| KR20160145572A (ko) | 2016-12-20 |
| EP3132469B1 (en) | 2019-01-09 |
| US20150294933A1 (en) | 2015-10-15 |
| CN106575623A (zh) | 2017-04-19 |
| BR112016023947A2 (pt) | 2017-08-15 |
| WO2015160671A1 (en) | 2015-10-22 |
| EP3132469A1 (en) | 2017-02-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161018 |
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| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180320 |
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| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180320 |
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| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20181217 |
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| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190121 |
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| A02 | Decision of refusal |
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