CN106575623A - 用于低剖面基板的图案间图案 - Google Patents

用于低剖面基板的图案间图案 Download PDF

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Publication number
CN106575623A
CN106575623A CN201580019675.3A CN201580019675A CN106575623A CN 106575623 A CN106575623 A CN 106575623A CN 201580019675 A CN201580019675 A CN 201580019675A CN 106575623 A CN106575623 A CN 106575623A
Authority
CN
China
Prior art keywords
patterned metal
metal layer
layer
substrates
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580019675.3A
Other languages
English (en)
Chinese (zh)
Inventor
H·B·蔚
C-K·金
D·W·金
J·S·李
K-P·黄
Y·K·宋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106575623A publication Critical patent/CN106575623A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
CN201580019675.3A 2014-04-15 2015-04-10 用于低剖面基板的图案间图案 Pending CN106575623A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/253,798 US9269610B2 (en) 2014-04-15 2014-04-15 Pattern between pattern for low profile substrate
US14/253,798 2014-04-15
PCT/US2015/025435 WO2015160671A1 (en) 2014-04-15 2015-04-10 Pattern between pattern for low profile substrate

Publications (1)

Publication Number Publication Date
CN106575623A true CN106575623A (zh) 2017-04-19

Family

ID=53005702

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580019675.3A Pending CN106575623A (zh) 2014-04-15 2015-04-10 用于低剖面基板的图案间图案

Country Status (7)

Country Link
US (1) US9269610B2 (enExample)
EP (1) EP3132469B1 (enExample)
JP (1) JP2017517142A (enExample)
KR (1) KR20160145572A (enExample)
CN (1) CN106575623A (enExample)
BR (1) BR112016023947A2 (enExample)
WO (1) WO2015160671A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109346821A (zh) * 2018-09-19 2019-02-15 中国科学院上海微系统与信息技术研究所 圆片级硅基集成小型化分形天线及其制备方法
US12044965B2 (en) * 2020-02-12 2024-07-23 Hutchinson Technology Incorporated Method for forming components without adding tabs during etching
US20220093505A1 (en) * 2020-09-24 2022-03-24 Intel Corporation Via connections for staggered interconnect lines
US12500162B2 (en) * 2021-12-22 2025-12-16 Intel Corporation Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition
US20230395506A1 (en) * 2022-06-06 2023-12-07 Intel Corporation Self-aligned staggered integrated circuit interconnect features

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2073951A (en) * 1980-04-11 1981-10-21 Hitachi Ltd Multilayer interconnections for an integrated circuit
US5136358A (en) * 1990-06-06 1992-08-04 Fuji Xerox Co., Ltd. Multi-layered wiring structure
GB2252668A (en) * 1991-02-05 1992-08-12 Samsung Electronics Co Ltd Interlayer contact structure
US6414367B1 (en) * 1999-10-28 2002-07-02 National Semiconductor Corporation Interconnect exhibiting reduced parasitic capacitance variation
JP2005236018A (ja) * 2004-02-19 2005-09-02 Alps Electric Co Ltd 微細配線構造および微細配線構造の製造方法
US20120097319A1 (en) * 2010-10-26 2012-04-26 Ngk Spark Plug Co., Ltd. Method of manufacturing multilayer wiring substrate
CN102986311A (zh) * 2010-07-08 2013-03-20 Lg伊诺特有限公司 印刷电路板及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299555A (ja) 2001-03-30 2002-10-11 Seiko Epson Corp 集積回路およびその製造方法
KR100808557B1 (ko) 2002-05-16 2008-02-29 매그나칩 반도체 유한회사 엠아이엠 캐패시터 형성방법
JP4559757B2 (ja) 2004-03-18 2010-10-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4769022B2 (ja) * 2005-06-07 2011-09-07 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP2007194476A (ja) 2006-01-20 2007-08-02 Shinko Electric Ind Co Ltd 多層配線基板の製造方法
US20110215465A1 (en) * 2010-03-03 2011-09-08 Xilinx, Inc. Multi-chip integrated circuit
US8377792B2 (en) * 2010-04-07 2013-02-19 National Semiconductor Corporation Method of forming high capacitance semiconductor capacitors with a single lithography step
US8722505B2 (en) * 2010-11-02 2014-05-13 National Semiconductor Corporation Semiconductor capacitor with large area plates and a small footprint that is formed with shadow masks and only two lithography steps
US8551856B2 (en) * 2011-09-22 2013-10-08 Northrop Grumman Systems Corporation Embedded capacitor and method of fabricating the same
US9012966B2 (en) * 2012-11-21 2015-04-21 Qualcomm Incorporated Capacitor using middle of line (MOL) conductive layers

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2073951A (en) * 1980-04-11 1981-10-21 Hitachi Ltd Multilayer interconnections for an integrated circuit
US5136358A (en) * 1990-06-06 1992-08-04 Fuji Xerox Co., Ltd. Multi-layered wiring structure
GB2252668A (en) * 1991-02-05 1992-08-12 Samsung Electronics Co Ltd Interlayer contact structure
US6414367B1 (en) * 1999-10-28 2002-07-02 National Semiconductor Corporation Interconnect exhibiting reduced parasitic capacitance variation
JP2005236018A (ja) * 2004-02-19 2005-09-02 Alps Electric Co Ltd 微細配線構造および微細配線構造の製造方法
CN102986311A (zh) * 2010-07-08 2013-03-20 Lg伊诺特有限公司 印刷电路板及其制造方法
US20120097319A1 (en) * 2010-10-26 2012-04-26 Ngk Spark Plug Co., Ltd. Method of manufacturing multilayer wiring substrate

Also Published As

Publication number Publication date
EP3132469A1 (en) 2017-02-22
US9269610B2 (en) 2016-02-23
EP3132469B1 (en) 2019-01-09
WO2015160671A1 (en) 2015-10-22
BR112016023947A2 (pt) 2017-08-15
US20150294933A1 (en) 2015-10-15
KR20160145572A (ko) 2016-12-20
WO2015160671A9 (en) 2016-06-09
JP2017517142A (ja) 2017-06-22

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Application publication date: 20170419

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