TW202011489A - 晶片封裝體的形成方法 - Google Patents

晶片封裝體的形成方法 Download PDF

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TW202011489A
TW202011489A TW108129546A TW108129546A TW202011489A TW 202011489 A TW202011489 A TW 202011489A TW 108129546 A TW108129546 A TW 108129546A TW 108129546 A TW108129546 A TW 108129546A TW 202011489 A TW202011489 A TW 202011489A
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Taiwan
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conductive
semiconductor die
layer
chip package
shielding
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TW108129546A
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English (en)
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莊博堯
蔡柏豪
鄭心圃
陳碩懋
游明志
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台灣積體電路製造股份有限公司
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Publication of TW202011489A publication Critical patent/TW202011489A/zh

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Abstract

提供晶片封裝體的結構及其形成方法。方法包含在承載基底上形成複數個導電結構。方法也包含在承載基底上設置半導體晶粒使得導電結構環繞半導體晶粒。方法更包含形成保護層以環繞導電結構和半導體晶粒。此外，方法包含在半導體晶粒和導電結構上設置屏蔽層。屏蔽層與導電結構電性連接。

Description

晶片封裝體的形成方法
本發明實施例是關於晶片封裝體的形成方法，特別是有關於具有屏蔽結構的晶片封裝體。
半導體裝置被用於各式各樣的電子應用中，例如個人電腦、手機、數位相機和其他電子設備。半導體裝置的製造包含在半導體基底上依序沉積絕緣或介電層、導電層和半導體層，且使用微影(lithography)和蝕刻製程將各種材料層圖案化以在半導體基底上形成電路組件及元件。
藉由持續地降低最小部件(feature)尺寸，半導體工業不斷在改善各種電子組件(例如電晶體、二極體、電阻、電容等)的整合密度，使得在給定的區域中允許整合更多的組件。顯著地增加輸入/輸出(input/output，I/O)連接。發展使用較少的區域或具有較低之高度的較小封裝結構以對半導體裝置進行封裝。
目前已發展新的封裝技術以進一步提升半導體裝置的密度和功能。這些相對較新型之半導體裝置的封裝技術面臨製造流程的挑戰。
根據本發明的一些實施例，提供晶片封裝體的形成方法。方法包含在承載基底上形成複數個導電結構。方法也包含在承載基底上設置半導體晶粒使得導電結構環繞半導體晶粒。此外，方法包含在半導體晶粒和導電結構上設置屏蔽層。屏蔽層與導電結構電性連接。
根據本發明的一些實施例，提供晶片封裝體的形成方法。方法包含在承載基底上形成屏蔽結構。方法也包含在承載基底上設置半導體晶粒使得屏蔽結構環繞半導體晶粒。屏蔽結構具有一或多個開口暴露出包含半導體晶粒的空間。方法更包含在承載基底上形成保護層使得一部分的保護層穿過前述之一或多個開口以環繞半導體晶粒。此外，方法包含在半導體晶粒和屏蔽結構上設置屏蔽層。屏蔽層與屏蔽結構電性連接。
根據本發明的一些實施例，提供晶片封裝體。晶片封裝體包含重佈線結構和在重佈線結構上的半導體晶粒。晶片封裝體也包含在半導體晶粒上的屏蔽層，以及在重佈線結構上的複數個導電結構。前述的導電結構環繞半導體晶粒且與屏蔽層電性連接。
根據本發明的一些實施例，提供晶片封裝體。晶片封裝體包含重佈線結構和在重佈線結構上的第一半導體晶粒與第二半導體晶粒。晶片封裝體也包含在第一半導體晶粒上的屏蔽層。晶片封裝體更包含在重佈線結構上的複數個導電結構。前述的導電結構環繞第一半導體晶粒放置的區域，第二半導體晶粒放置在此區域外。
以下揭露提供了很多不同的實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本揭露的說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，以下敘述中提及第一部件形成於第二部件之上或上方，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本揭露在各種範例中可能重複參考數字及/或字母，此重複是為了簡化和清楚，並非在討論的各種實施例及/或組態之間指定其關係。
再者，空間上相關的用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用語可用於此，使得描述圖中所示之一元件或部件與其他元件或部件之間的關係更加地容易。此空間上相關的用語可涵蓋除圖式描繪之方向外，使用或操作中的裝置之不同方向。設備可以其他方向定位(旋轉90度或其他方向)，且在此使用的空間相關描述可同樣依此解讀。
本發明的一些實施例是與三維(three dimensional，3D)封裝或三維-積體電路(three dimensional integrated circuit，3D-IC)裝置有關。本發明的一些實施例也可包含其他部件和製程。舉例而言，可包含測試結構(testing structure)以幫助對於三維封裝或三維積體電路裝置進行的驗證測試。測試結構可例如包含形成於重佈線層內或形成於基底上的測試接墊(test pad)，以便能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構和最終結構進行驗證測試。另外，可將本文所揭露的結構和方法與包含對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
以下描述了本發明的一些實施例。可在下述實施例之步驟的前、中、後提供額外的操作。以下描述的一些步驟可在不同的實施例中被取代或刪除。可在半導體裝置結構中加入額外的部件。以下描述的一些部件可在不同的實施例中被取代或刪除。雖然在此討論的一些實施例及操作是以特定的順序予以實施，然而，這些操作可以其他的邏輯順序予以實施。
第1A-1F圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。根據一些實施例，如第1A圖所示，在承載基底100上形成互連結構102。互連結構102可作為佈線(routing)所用的重佈線結構。如第1A圖所示，互連結構102包含多個絕緣層104和多個導電部件106。導電部件106可包含導線(conductive line)、導孔(conductive via)及/或導電墊。互連結構102也包含用於承載或接收其他元件(例如導電柱或半導體晶粒(die))的導電部件107。
一些實施例中，一些導電部件107係暴露於絕緣層104的最頂面，或自絕緣層104的最頂面突出。暴露出或突出的導電部件107可作為後續將形成之導電凸塊(例如含錫的焊料凸塊)及/或導電柱(例如銅柱)的接合墊。
絕緣層104可由一或多個高分子材料製成，或者包含一或多個高分子材料。高分子材料可包含聚苯並噁唑(polybenzoxazole，PBO)、聚亞醯胺(polyimide，PI)、雙-苯環丁烯(benzocyclobutenes，BCB)、一或多個其他合適的高分子材料、或前述之組合。一些實施例中，高分子材料是感光性的。一些實施例中，一些或全部的絕緣層104係由非高分子材料的介電材料製成，或者包含非高分子材料的介電材料。介電材料可包含氧化矽、碳化矽、氮化矽、氮氧化矽、一或多個其他合適的材料，或前述之組合。
導電部件106可包含提供水平方向上之電性連接的導線，以及提供垂直方向上之電性連接的導孔。導電部件106可由銅、鋁、金、鈷、鈦、石墨烯(graphene)、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。
互連結構102的形成可包含多道沉積或塗佈製程、多道圖案化製程及/或多道平坦化製程。
沉積或塗佈製程可用於形成絕緣層及/或導電層。沉積或塗佈製程可包含旋轉塗佈(spin coating)製程、電鍍(electroplating)製程、無電(electroless)電鍍製程、化學氣相沉積(chemical vapor deposition，CVD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、原子層沉積(atomic layer deposition，ALD)製程、一或多個其他合適的製程、或前述之組合。
圖案化製程可用於將已形成的絕緣層及/或已形成的導電層圖案化。圖案化製程可包含微影製程、能量束鑽孔(energy beam drilling)製程(例如雷射(laser)束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、蝕刻製程、機械鑽孔製程、一或多個其他合適的製程、或前述之組合。
平坦化製程可用於對已形成的絕緣層及/或已形成的導電層提供平坦的頂面，以促進後續的製程。平坦化製程可包含機械研磨製程、化學機械拋光(chemical mechanical polishing，CMP)製程、一或多個其他合適的製程、或前述之組合。
然而，本揭露的實施例可具有多種變化及/或調整。一些其他的實施例中並未形成互連結構102。
隨後，根據一些實施例，如第1A圖所示，在一些導電部件107上形成導電結構108和108S(又稱為接地結構或導電接地結構)。一些實施例中，導電結構108係用於訊號傳輸。一些實施例中，導電結構108S係作為屏蔽(shielding)結構，能避免後續將設置的半導體晶粒所產生的電磁干擾(electromagnetic interference，EMI)。
一些實施例中，導電結構108和108S為導電柱。一些實施例中，導電結構108和108S具有大抵上直的側壁。導電結構108和108S的側壁可大抵上垂直於承載基底100的頂表面。導電結構108和108S可由銅、鋁、鈦、鈷、金、含錫合金、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。
導電結構108和108S的形成可使用電鍍製程、無電電鍍製程、物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、一或多個其他合適的製程、或前述之組合。一些其他的實施例中，將導電結構108和108S取放(pick and place)於暴露的導電部件107上。含錫的焊料元件可用於固定導電結構108和108S。一些實施例中，同時形成導電結構108和108S。一些其他的實施例中，分別形成導電結構108和108S。舉例而言，導電結構108係在導電結構108S之前形成的。或者，導電結構108S係在導電結構108之前形成的。
根據一些實施例，如第1B圖所示，在承載基底100上設置半導體裝置，例如半導體晶粒110A和110B。如第1B圖所示，半導體晶粒110B係設置於由導電結構108S所環繞的區域之外。
一些實施例中，半導體晶粒110A和110B(又稱為元件)係設置於一些暴露的導電部件107上。半導體晶粒110A和110B可為系統單晶片(system-on-chip，SoC)之晶片。一些其他的實施例中，元件110A和110B為具有整合功能、包含兩個或更多晶片的系統積體電路(system on integrated circuit，SoIC)裝置。在這些例子中，參考符號「110A或110B」係用以指稱半導體裝置。半導體裝置可包含一個晶粒、多個晶粒、或系統積體電路晶片裝置。舉例而言，一個或兩個元件110A和110B包含多個半導體晶粒的堆疊。
一些實施例中，半導體晶粒110A包含射頻積體電路(radio-frequency integrated circuit，RF-IC)，例如射頻前端(radio-frequency front end，RFFE)模組。半導體晶粒110A的操作頻率在射頻範圍內。半導體晶粒110A在操作期間可產生波長相應於操作頻率的電磁波。
舉例而言，半導體晶粒110A的操作頻率可約為28千兆赫(GHz)。在這些例子中，半導體晶粒110A在操作期間可產生波長約為10.7毫米(mm)的電磁波。舉例而言，電磁波可通過保護基底20的天線層207進行訊號發送或接收。一些例子中，產生的電磁波可能對附近的裝置元件的運作產生負面的影響(例如半導體晶粒100B或在附近之其他晶片封裝體內的其他裝置元件)。一些實施例中，後續將形成屏蔽結構及/或屏蔽層以避免產生的電磁波傳送至附近的裝置元件並影響附近的裝置元件的運作。
一些實施例中，半導體晶粒110B包含低雜訊放大器(low-noise amplifier，LNA)模組、低損耗濾波器(low-loss filter)模組、功率放大器(power amplifier，PA)模組、基頻(baseband)模組、電源管理積體電路(power management integrated circuit，PMIC)、記憶體模組、微機電系統 (micro-electromechanical system，MEMS) 模組、奈米機電系統(nano-electromechanical system，NEMS)模組、一或多個其他合適的電路、或前述之組合。一些實施例中，半導體晶粒110B並未包含任何射頻積體電路。
一些實施例中，在承載基底100上的互連結構102上設置半導體晶粒110A和110B。一些實施例中，半導體晶粒110A和110B藉由接合結構114與互連結構102的一些導電部件107接合。接合結構114可與半導體晶粒110A和110B的一些導電部件107和導電部件112進行物理上和電性上的連接。半導體晶粒110A和110B的導電部件112可包含導電墊、導電柱、導電線路或前述之相似導電結構。
一些實施例中，接合結構114為焊料凸塊，例如含錫的焊料凸塊，或者包含上述材料。含錫的焊料凸塊可更包含銅、銀、金、鋁、鉛、一或多個其他合適的材料、或前述之組合。一些實施例中，含錫的焊料凸塊不含鉛。接合結構114的形成方法可包含一或多道回流(reflow)製程及/或一或多道電鍍製程。
根據一些實施例，如第1B圖所示，形成底部填充(underfill)元件116以保護接合結構114。底部填充元件116由一或多個高分子材料製成，或者包含一或多個高分子材料。底部填充元件116可包含以環氧樹脂為基底的樹脂(epoxy-based resin)。一些實施例中，底部填充元件116更包含填充物(filler)分散於以環氧樹脂為基底的樹脂之中。一些實施例中，底部填充元件116的形成包含射出成型(injecting)製程、點膠(dispensing)製程、薄膜貼合(film lamination)製程、應用製程、一或多個其他合適的製程、或前述之組合。一些實施例中，接著使用熱固化(thermal curing)製程以完成底部填充元件116的形成。
根據一些實施例，如第1C圖所示，提供或接收保護基底20，且保護基底20係準備好可接合於導電結構108和108S上的。一些實施例中，保護基底20包含板材200和屏蔽層208(又稱為屏蔽元件)。一些實施例中，保護基底20也包含導電元件214和214S。一些實施例中，保護基底20包含天線層、主貼片(main patch)元件、寄生貼片(parasitic patch)元件、接地層、一或多個其他合適的元件、或前述之組合。
第2A-2E圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。一些實施例中，第1C圖中的保護基底20係使用如第2A-2E圖所示的製程以形成。
根據一些實施例，如第2A圖所示，在板材200相對兩側的表面上形成導電膜202A和202B。導電膜202A和202B可在後續的電鍍製程中給予幫助。板材200可由高分子材料、陶瓷材料、金屬材料、半導體材料、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。舉例而言，板材200包含樹脂、預浸材(prepreg)、玻璃及/或陶瓷。
導電膜202A和202B可由鋁、銅、鈷、金、鈦、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。導電膜202A和202B的形成可使用熱壓(thermal compression)製程、物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、貼合(lamination)製程、印刷製程、一或多個其他合適的製程、或前述之組合。
然而，本揭露的實施例不限於此。一些其他的實施例中並未形成導電膜202A和202B。
根據一些實施例，如第2B圖所示，將導電膜202A和202B以及板材200部分地移除以形成開口204。一些實施例中，開口204完全穿過板材200以及導電膜202A和202B。開口204的形成可使用能量束鑽孔製程、機械鑽孔製程、微影及蝕刻製程、一或多個其他合適的製程、或前述之組合。能量束鑽孔製程可包含雷射鑽孔製程、離子束鑽孔製程、電子束鑽孔製程、電漿束鑽孔製程、一或多個其他合適的製程、或前述之組合。
隨後，根據一些實施例，在第2B圖所示之結構上沉積晶種層。晶種層延伸至導電膜202A和202B上。晶種層更延伸至開口204的側壁上。隨後，在晶種層上形成圖案化的光阻層。圖案化的光阻層具有部分暴露出晶種層的開口，這些開口定義出後續將要形成在板材200上的導電部件的圖案。然後，在未被圖案化的光阻層覆蓋之部分的晶種層上電鍍形成一或多個導電材料。隨後，移除圖案化的光阻層。使用一或多道蝕刻製程以移除原本由圖案化的光阻層所覆蓋之部分的晶種層。在進行一或多道蝕刻製程的期間也移除原本由圖案化的光阻層所覆蓋之部分的導電膜202A和202B。
結果，根據一些實施例，如第2C圖所示，部分地暴露出板材200。電鍍形成的導電材料的剩餘部分、晶種層的剩餘部分、以及導電膜202A和202B的剩餘部分共同形成具有預期圖案的導電部件206。一些導電部件206穿透板材200以提供放置在板材200相對兩側之表面上的元件之間的電性連接。
一些實施例中，如第2C圖所示，一些導電部件206共同形成一個(或多個)天線層207(又稱為天線結構或天線元件)。可對天線層207的圖案進行微調以提供預期的功能。一些實施例中，天線層207為在法線方向(normal direction)上用於接收及/或傳送電磁訊號的天線(例如貼片天線(patch antenna))。一些其他的實施例中，天線層207為在側向(side direction)上用於接收及/或傳送電磁訊號的端射(end-fire)天線。一些實施例中，在板材200上形成具有不同功能的多個天線層。
根據一些實施例，如第1C圖所示，在板材200的底表面上形成屏蔽層208。一些實施例中，一或多個導電部件206形成屏蔽層208。在這些例子中，將相同的導電材料層圖案化以形成天線層207和屏蔽層208。天線層207和屏蔽層208係由相同的材料製成。一些其他的實施例中，使用不同的製程以形成天線層207和屏蔽層208。一些實施例中，屏蔽層208和天線層207係由不同的材料製成。
根據一些實施例，如第2D圖所示，在板材200相對兩側的表面上形成保護層210和212。保護層210和212可由以環氧樹脂為基底的樹脂、聚亞醯胺(PI)、聚苯並噁唑(PBO)、一或多個其他合適的材料、或前述之組合製成，或者包含上述的材料。保護層210和212具有部分暴露出導電部件206的多個開口。舉例而言，如第2D圖所示，部分地暴露出天線層207和屏蔽層208。保護層210和212的形成方法包含塗佈製程和微影製程。塗佈製程可包含旋轉塗佈製程、噴塗(spray coating)製程、貼合製程、一或多個其他合適的製程、或前述之組合。
根據一些實施例，如第2E圖所示，在一些導電部件206上形成導電元件214(又稱為導電凸塊)。一些實施例中，如第2D圖所示，在屏蔽層208暴露出的部分上形成導電元件214S(又稱為導電凸塊)。一些實施例中，導電凸塊214和214S係由相同的材料製成。一些實施例中，導電凸塊214和214S為含錫的焊料元件。含錫的焊料元件可更包含銅、銀、金、鋁、鉛、一或多個其他合適的材料、或前述之組合。一些實施例中，含錫的焊料元件不含鉛。導電凸塊214和214S的形成可包含一或多道鍍覆製程(例如電鍍製程)及/或一或多道回流製程。隨後，可執行分割(singulation)製程以對結構進行裁切。結果形成多個保護基底20。在第2E圖中顯示一個保護基底20。
根據一些實施例，再往回參見第1C圖，放置保護基底20使得導電元件214大抵上對齊於導電結構108。保護基底20的放置也使得導電元件214S大抵上對齊於導電結構108S。如上所述，一些實施例中，導電元件214和214S為含錫的焊料元件，可促進後續的接合製程。
根據一些實施例，如第1D圖所示，將保護基底20與導電結構108和108S接合。一些實施例中，保護基底20藉由導電凸塊214和214S與導電結構108和108S接合。如上所述，一些實施例中，導電凸塊214和214S為含錫的焊料凸塊。可使用回流製程以將導電凸塊214和214S分別與導電結構108和108S接合。一些實施例中，在將保護基底20與導電結構214和214S接合之後，也將屏蔽層208設置在半導體晶粒110A上。屏蔽層208藉由導電凸塊214S與導電結構108S電性連接。
屏蔽層208和共同作為屏蔽結構的多個導電結構108S可以避免半導體晶粒110A產生的電磁波影響附近的裝置元件(例如半導體晶粒110B或其他附近的封裝體)的運作。一些其他未形成導電結構108S或屏蔽層208的例子中，半導體晶粒110A產生的電磁波可對半導體晶粒110B的運作或其他附近的裝置元件的運作產生負面影響。
第3圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。一些實施例中，第3圖顯示第1B圖所示之結構的上視圖。為了簡化及清楚說明，僅顯示屏蔽結構、最上層的絕緣層104以及半導體晶粒110A和110B。
根據一些實施例，如第3圖所示，導電結構108S環繞或包圍半導體晶粒110A所放置的空間。半導體晶粒110B係放置於導電結構108S所環繞的區域之外。一些實施例中，每一個導電結構108S在上視圖中皆具有圓形的輪廓。這些導電結構108S共同形成屏蔽結構。屏蔽結構具有暴露出包含半導體晶粒110A之空間的多個開口G。因此，在後續形成保護層的製程中，一部分的保護層可穿過開口G以環繞和保護半導體晶粒110A。
一些實施例中，如第3圖所示，兩個相鄰的導電結構108S彼此分隔一段距離W1 。距離W1 可在約10微米(μm)至半導體晶粒110A所產生之電磁波波長的一半的範圍內。如第3圖所示，每一個導電結構108S具有寬度W2 。一些實施例中，寬度W2 在約5 μm至約距離W1 之十倍的範圍內，以確保具有足夠的屏蔽效果。
一些例子中，若距離W1 小於約10 μm，隨後形成的保護層將無法穿過開口G以保護半導體晶粒110A。或者，隨後形成的保護層將無法完全地環繞和保護半導體晶粒110A，對晶片封裝體的可靠度和品質將產生負面影響。
一些其他的例子中，若距離W1 大於半導體晶粒110A所產生之電磁波波長的一半，屏蔽效果可能不足。結果可能導致半導體晶粒110A在操作中產生的電磁波無法受到良好地屏蔽，且可能傳送至附近的裝置元件(例如半導體晶粒110B或其他附近的封裝體)進而對運作產生負面影響。
舉例而言，半導體晶粒110A的操作頻率可約為28 GHz。在這些例子中，半導體晶粒110A在操作期間可產生波長約為10.7 mm的電磁波。在這些例子中，半導體晶粒110A產生的電磁波波長的一半約為5.35 mm。一些實施例中，距離W1 係設定在約10 μm至約5.35 mm的範圍內以確保具有足夠的屏蔽效果，並確保半導體晶粒110A能受到足夠的保護。一些實施例中，寬度W2 係設定在約5 μm至約53.5 mm的範圍內。
然而，本揭露的實施例不限於此。本揭露的實施例可具有多種變化及/或調整。不同的導電結構的上視圖可具有不同的形狀。
第4圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。一些實施例中，第4圖顯示第1B圖所示之結構的上視圖。為了簡化及清楚說明，僅顯示屏蔽結構、最上層的絕緣層104以及半導體晶粒110A和110B。
根據一些實施例，如第4圖所示，半導體晶粒110A不只由導電結構108S所環繞，也由導電牆108S’所環繞。一些實施例中，導電牆108S’的側向延伸方向大抵上平行於半導體晶粒110A側邊的側向延伸方向。導電結構108S和導電牆108S’共同作為屏蔽結構。
屏蔽結構具有暴露出包含半導體晶粒110A之空間的多個開口G。因此，在後續形成保護層的製程中，一部分的保護層可穿過開口G以環繞和保護半導體晶粒110A。一些實施例中，任何相鄰的導電結構108S及/或導電牆108S’之間的距離在約10 μm至半導體晶粒110A所產生之電磁波波長的一半的範圍內。
本揭露的實施例可具有多種變化及/或調整。第5圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。一些實施例中，第5圖顯示第1B圖所示之結構的上視圖。為了簡化及清楚說明，僅顯示屏蔽結構、最上層的絕緣層104以及半導體晶粒110A和110B。
一些實施例中，如第5圖所示，每一個導電結構108S在上視圖中皆具有橢圓形的輪廓。這些導電結構108S共同形成屏蔽結構。屏蔽結構具有暴露出包含半導體晶粒110A之空間的多個開口G。因此，在後續形成保護層的製程中，一部分的保護層可穿過開口G以環繞和保護半導體晶粒110A。一些實施例中，任何相鄰的導電結構108S及/或導電牆108S’之間的距離在約10 μm至半導體晶粒110A所產生之電磁波波長的一半的範圍內。
本揭露的實施例可具有多種變化及/或調整。第6圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。一些實施例中，第6圖顯示第1B圖所示之結構的上視圖。為了簡化及清楚說明，僅顯示屏蔽結構、最上層的絕緣層104以及半導體晶粒110A和110B。
一些實施例中，半導體晶粒110A由作為屏蔽結構的單一個導電牆108S’’所環繞。屏蔽結構具有暴露出包含半導體晶粒110A之空間的開口G。因此，在後續形成保護層的製程中，一部分的保護層可穿過開口G以環繞和保護半導體晶粒110A。一些實施例中，開口G的寬度在約10 μm至半導體晶粒110A所產生之電磁波波長的一半的範圍內。
本揭露的實施例可具有多種變化及/或調整。第7圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。一些實施例中，第7圖顯示第1B圖所示之結構的上視圖。為了簡化及清楚說明，僅顯示屏蔽結構、最上層的絕緣層104以及半導體晶粒110A和110B。
一些實施例中，如第7圖所示，每一個導電結構108S在上視圖中皆具有橢圓形的輪廓。一些實施例中，如第7圖所示，一個或每一個導電結構108S的長軸係沿著大抵上平行於半導體晶粒110A相應之側邊的延伸方向上延伸。
這些導電結構108S共同形成屏蔽結構。屏蔽結構具有暴露出包含半導體晶粒110A之空間的多個開口G。因此，在後續形成保護層的製程中，一部分的保護層可穿過開口G以環繞和保護半導體晶粒110A。一些實施例中，任何相鄰的導電結構108S及/或導電牆108S’之間的距離在約10 μm至半導體晶粒110A所產生之電磁波波長的一半的範圍內。
一些實施例中，如上所述，屏蔽結構及屏蔽層208彼此電性連接。因此，屏蔽結構(包含導電結構108S及/或導電牆108S’)和屏蔽層208可一起降低或避免半導體晶粒110A所產生的電磁干擾(EMI)現象。根據一些實施例，屏蔽層208可具有多種變化及/或調整。舉例而言，屏蔽層208在上視圖中可具有許多變化。
第14圖是根據一些實施例，顯示晶片封裝體之屏蔽層的上視圖。一些實施例中，第14圖顯示出第1D圖所示之屏蔽層208的上視圖。一些實施例中，屏蔽層208為導電板。一些實施例中，導電板不具有開口或穿孔。一些實施例中，屏蔽層208覆蓋屏蔽結構(包含導電結構108S及/或導電牆108S’)和半導體晶粒110A。
本揭露的實施例可具有多種變化及/或調整。第15圖是根據一些實施例，顯示晶片封裝體之屏蔽層的上視圖。一些實施例中，屏蔽層208為具有許多穿孔G’的導電網狀物(mesh)。一些實施例中，每一個穿孔G’係設定為具有寬度W3 ，且寬度W3 在約10 μm至半導體晶粒110A所產生之電磁波波長的一半的範圍內。因此可確保屏蔽層208的屏蔽效率。
一些其他的實施例中，屏蔽層208包含導電板和導電網狀物的組合。舉例而言，屏蔽層208的一部分為不具有穿孔G’的導電板，而屏蔽層208的另一部分為具有穿孔G’的導電網狀物。
根據一些實施例，如第1E圖所示，形成環繞半導體晶粒110A和110B以及導電結構108S和108的保護層118。一些實施例中，保護層118穿過在導電結構108S之間的開口G(如第3、4、5、6或7圖所示)以環繞半導體晶粒110A。一些實施例中，保護層118直接接觸導電結構108和108S。一些實施例中，保護層118直接接觸半導體晶粒110A和110B。一些實施例中，保護層118的一部分在半導體晶粒110A與屏蔽層208之間。
一些實施例中，保護層118的材料與板材200的材料不同。一些實施例中，保護層118的介電常數大於板材200的介電常數。一些實施例中，保護層118的損耗因數(dissipation factor)大於板材200的損耗因數。
一些實施例中，保護層118由模塑化合物材料製成，或包含模塑化合物材料。模塑化合物材料可包含高分子材料，例如具有填充物分散於其中的以環氧樹脂為基底的樹脂。一些實施例中，在保護基底20與承載基底100之間導入或注入液態的模塑化合物材料。液態的模塑化合物材料可流入開口G內以密封半導體晶粒110A。然後使用熱處理製程以將液態的模塑化合物材料固化，並將其轉變為保護層118。
根據一些實施例，如第1F圖所示，移除承載基底100，並形成導電凸塊120。一些實施例中，導電凸塊120為焊料凸塊，例如含錫的焊料凸塊，或者包含上述材料。含錫的焊料凸塊可更包含銅、銀、金、鋁、鉛、一或多個其他合適的材料、或前述之組合。一些實施例中，含錫的焊料凸塊不含鉛。一些實施例中，在移除承載基底100之後，在暴露的導電部件106上設置焊球(或焊料元件)。然後執行回流製程以將焊球熔化為導電凸塊120。一些其他的實施例中，在設置焊球之前，在暴露的導電部件106上形成凸塊下金屬化 (under bump metallization，UBM) 元件。一些其他的實施例中，在暴露的導電部件106上電鍍形成焊料元件。隨後，使用回流製程以將焊料元件熔化為導電凸塊120。一些實施例中，接著執行分割製程以對形成的結構進行裁切。結果形成多個分離的晶片封裝體。在第1F圖中顯示一個晶片封裝體。
本揭露的實施例可具有多種變化及/或調整。第8A-8C圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。根據一些實施例，如第8A圖所示，提供或形成相似於第1C圖所示之結構。
一些實施例中，如第8A圖所示，在保護基底20與導電結構108和108S接合之前，在半導體晶粒110A和110B上形成黏著元件802。黏著元件802可包含黏著膠帶、黏著膠或其他合適的元件。
根據一些實施例，如第8B圖所示，將保護基底20與導電結構108和108S接合。一些實施例中，保護基底20藉由導電凸塊214和214S與導電結構108和108S接合。黏著元件802可幫助接合製程以避免未對準(misalignment)及/或不預期的位移發生。
隨後，根據一些實施例，如第8C圖所示，使用相似或相同於第1E和1F圖之製程以形成晶片封裝體。
本揭露的實施例可具有多種變化及/或調整。第9圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。一些實施例中，晶片封裝體包含由導電結構108S和屏蔽層208所環繞的單一半導體晶粒(半導體晶粒110A)。
本揭露的實施例可具有多種變化及/或調整。第10圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。一些實施例中，晶片封裝體包含由導電結構108S和屏蔽層208所環繞的單一半導體晶粒(半導體晶粒110A)。如第10圖所示，黏著元件802係形成於半導體晶粒110A與屏蔽層208之間。
本揭露的實施例可具有多種變化及/或調整。第11圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。一些實施例中，提供或形成相同或相似於第8C圖所示之結構。隨後，將此結構與電路板804接合。一些實施例中，電路板804為印刷電路板。一些實施例中，電路板804包含屏蔽層806。
相似於屏蔽層208，屏蔽層806可為導電板、導電網狀物、或前述之組合。屏蔽層806可用以進一步地增加屏蔽效果。屏蔽層元件208和共同作為屏蔽結構的多個導電結構108S可一起用於避免半導體晶粒110A產生的電磁波影響附近的裝置元件(例如半導體晶粒110B或其他附近的封裝體)的運作。
一些實施例中，在板材200與半導體晶粒110A之間形成屏蔽層208。然而，本揭露的實施例不限於此。本揭露的實施例可具有多種變化及/或調整。一些其他的實施例中，在其他位置形成屏蔽層。
第12圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。一些實施例中，形成屏蔽層208’。屏蔽層208’具有位於板材200上的第一部分，以及穿過板材200的第二部分。因此，在這些例子中，板材200係位於屏蔽層208’的第一部分與半導體晶粒110A之間。屏蔽層208’的第一部分藉由導電元件214S和屏蔽層208’的第二部分與導電結構108S電性連接。屏蔽層208’的材料和形成方法可相同或相似於屏蔽層208及/或導電部件206的材料和形成方法。相似於屏蔽層208，屏蔽層806可為導電板、導電網狀物、或前述之組合。
本揭露的實施例可具有多種變化及/或調整。第13圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。第13圖顯示相似於第11圖之晶片封裝體的剖面示意圖。一些實施例中，晶片封裝體更包含一個(或多個)被動組件902。被動組件902可包含電阻、電容、電感、一或多個其他合適的元件、或前述之組合。
本揭露的實施例可具有多種變化及/或調整。舉例而言，可調整天線層的位置及/或數量。一些實施例中，一些導電部件106共同作為一個天線層。一些實施例中，一些導電結構108作為一個天線層。一些實施例中，形成多個天線層。
本揭露的實施例形成具有屏蔽結構的晶片封裝體。形成一個或多個導電結構以環繞半導體晶粒預定要放置的區域。半導體晶粒可包含射頻電路，且可在操作期間產生電磁波。導電結構環繞半導體晶粒且作為屏蔽結構。因此，可避免產生的電磁波對附近的裝置元件產生負面影響，可顯著地改善晶片封裝體的品質和效能。
根據本發明的一些實施例，提供晶片封裝體的形成方法。方法包含在承載基底上形成複數個導電結構。方法也包含在承載基底上設置半導體晶粒使得導電結構環繞半導體晶粒。此外，方法包含在半導體晶粒和導電結構上設置屏蔽層。屏蔽層與導電結構電性連接。
在一實施例中，晶片封裝體的形成方法更包含形成保護層以環繞導電結構和半導體晶粒，以及在形成保護層之前，將保護基底與導電結構接合。
在一實施例中，晶片封裝體的形成方法更包含在將保護基底與導電結構皆和之前，在保護基底上形成屏蔽層。
在一實施例中，晶片封裝體的形成方法更包含在保護基底上形成天線層。
在一實施例中，其中在將保護基底與導電結構接合之前，在保護基底上形成天線層。
在一實施例中，其中保護基底藉由含錫的焊料元件與導電結構接合。
在一實施例中，晶片封裝體的形成方法更包含在保護基底與承載基底之間導入高分子材料，以及將高分子材料固化以形成保護層。
在一實施例中，晶片封裝體的形成方法更包含在形成導電結構之前，在承載基底上形成重佈線結構。
在一實施例中，晶片封裝體的形成方法更包含移除承載基底，以及在重佈線結構上形成導電凸塊，其中重佈線結構在保護層與導電凸塊之間。
在一實施例中，晶片封裝體的形成方法更包含在形成保護層之前，在承載基底上設置第二半導體晶粒，其中第二半導體晶粒在導電結構環繞的區域外。
根據本發明的一些實施例，提供晶片封裝體。晶片封裝體包含重佈線結構和在重佈線結構上的第一半導體晶粒與第二半導體晶粒。晶片封裝體也包含在第一半導體晶粒上的屏蔽層。晶片封裝體更包含在重佈線結構上的複數個導電結構。前述的導電結構環繞第一半導體晶粒放置的區域，第二半導體晶粒放置在此區域外。
在一實施例中，其中導電結構中的兩者彼此相隔一段距離，此距離小於第一半導體晶粒產生的電磁波波長的一半。
在一實施例中，其中屏蔽層包含具有複數個穿孔的導電網狀物，且每一個穿孔具有寬度，此寬度小於第一半導體晶粒產生的電磁波波長的一半。
在一實施例中，其中導電結構藉由含錫的焊料元件與屏蔽層電性連接。
在一實施例中，封裝結構更包含環繞第一半導體晶粒和第二半導體晶粒的保護層，其中保護層直接接觸導電結構。
根據本發明的一些實施例，提供晶片封裝體。晶片封裝體包含重佈線結構和在重佈線結構上的半導體晶粒。晶片封裝體也包含在半導體晶粒上的屏蔽層，以及在重佈線結構上的複數個導電結構。前述的導電結構環繞半導體晶粒且與屏蔽層電性連接。
在一實施例中，屏蔽層包含導電板、導電網狀物、或前述之組合。
在一實施例中，其中導電結構中的兩者彼此相隔一段距離，此距離在約10 μm至半導體晶粒產生的電磁波波長的一半的範圍內。
在一實施例中，其中導電結構中的一者具有寬度，此寬度在約5 μm至約前述之距離的十倍的範圍內。
在一實施例中，晶片封裝體更包含在重佈線結構下的板材，以及形成在板材內的第二屏蔽層，其中第二屏蔽層藉由導電結構與屏蔽層電性連接。
以上概述數個實施例或範例之特徵，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例或範例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍之下，做各式各樣的改變、取代和替換。
20:保護基底； 100:承載基底； 102:互連結構； 104:絕緣層； 106、107、206:導電部件； 108、108S:導電結構； 108S’、108S’’: 導電牆； 110A、110B:半導體晶粒； 114:接合結構； 116:底部填充元件； 118、210、212:保護層； 120:導電凸塊； 200:板材； 202A、202B:導電膜； 204:開口； 207:天線層； 208、208’、806:屏蔽層； 214、214S:導電元件； 802:黏著元件； 804:電路板； 902:被動組件； G:開口； G’:穿孔； W1:距離； W2、W3:寬度。
藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的內容。需注意的是，根據產業上的標準做法，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，這些部件的尺寸可能被任意地增加或減少。 第1A-1F圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。 第2A-2E圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。 第3圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。 第4圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。 第5圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。 第6圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。 第7圖是根據一些實施例，顯示形成晶片封裝體之製程中間階段的上視圖。 第8A-8C圖是根據一些實施例，顯示形成晶片封裝體之製程中各個階段的剖面示意圖。 第9圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。 第10圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。 第11圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。 第12圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。 第13圖是根據一些實施例，顯示晶片封裝體的剖面示意圖。 第14圖是根據一些實施例，顯示晶片封裝體之屏蔽層的上視圖。 第15圖是根據一些實施例，顯示晶片封裝體之屏蔽層的上視圖。
20:保護基底
102:互連結構
104:絕緣層
106、107、206:導電部件
108、108S:導電結構
118、210、212:保護層
120:導電凸塊
200:板材
207:天線層
208:屏蔽層
214、214S:導電元件

Claims (1)

  1. 一種晶片封裝體的形成方法，包括： 在一承載基底上形成複數個導電結構； 在該承載基底上設置一半導體晶粒使得該些導電結構環繞該半導體晶粒；以及 在該半導體晶粒和該些導電結構上設置一屏蔽層，其中該屏蔽層與該些導電結構電性連接。
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