JP2017517142A5 - - Google Patents

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Publication number
JP2017517142A5
JP2017517142A5 JP2016562244A JP2016562244A JP2017517142A5 JP 2017517142 A5 JP2017517142 A5 JP 2017517142A5 JP 2016562244 A JP2016562244 A JP 2016562244A JP 2016562244 A JP2016562244 A JP 2016562244A JP 2017517142 A5 JP2017517142 A5 JP 2017517142A5
Authority
JP
Japan
Prior art keywords
metal layer
patterned metal
layer
substrate
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016562244A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017517142A (ja
Filing date
Publication date
Priority claimed from US14/253,798 external-priority patent/US9269610B2/en
Application filed filed Critical
Publication of JP2017517142A publication Critical patent/JP2017517142A/ja
Publication of JP2017517142A5 publication Critical patent/JP2017517142A5/ja
Pending legal-status Critical Current

Links

JP2016562244A 2014-04-15 2015-04-10 低背基板のためのパターン間パターン Pending JP2017517142A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/253,798 US9269610B2 (en) 2014-04-15 2014-04-15 Pattern between pattern for low profile substrate
US14/253,798 2014-04-15
PCT/US2015/025435 WO2015160671A1 (en) 2014-04-15 2015-04-10 Pattern between pattern for low profile substrate

Publications (2)

Publication Number Publication Date
JP2017517142A JP2017517142A (ja) 2017-06-22
JP2017517142A5 true JP2017517142A5 (enExample) 2018-05-10

Family

ID=53005702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016562244A Pending JP2017517142A (ja) 2014-04-15 2015-04-10 低背基板のためのパターン間パターン

Country Status (7)

Country Link
US (1) US9269610B2 (enExample)
EP (1) EP3132469B1 (enExample)
JP (1) JP2017517142A (enExample)
KR (1) KR20160145572A (enExample)
CN (1) CN106575623A (enExample)
BR (1) BR112016023947A2 (enExample)
WO (1) WO2015160671A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109346821A (zh) * 2018-09-19 2019-02-15 中国科学院上海微系统与信息技术研究所 圆片级硅基集成小型化分形天线及其制备方法
US12044965B2 (en) * 2020-02-12 2024-07-23 Hutchinson Technology Incorporated Method for forming components without adding tabs during etching
US20220093505A1 (en) * 2020-09-24 2022-03-24 Intel Corporation Via connections for staggered interconnect lines
US20230395506A1 (en) * 2022-06-06 2023-12-07 Intel Corporation Self-aligned staggered integrated circuit interconnect features

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3114679A1 (de) * 1980-04-11 1982-01-14 Hitachi, Ltd., Tokyo Integrierte schaltung mit mehrschichtenverbindungen
JPH0750710B2 (ja) 1990-06-06 1995-05-31 富士ゼロックス株式会社 多層配線構造
KR920017227A (ko) 1991-02-05 1992-09-26 김광호 반도체장치의 층간콘택 구조 및 그 제조방법
US6414367B1 (en) 1999-10-28 2002-07-02 National Semiconductor Corporation Interconnect exhibiting reduced parasitic capacitance variation
JP2002299555A (ja) 2001-03-30 2002-10-11 Seiko Epson Corp 集積回路およびその製造方法
KR100808557B1 (ko) 2002-05-16 2008-02-29 매그나칩 반도체 유한회사 엠아이엠 캐패시터 형성방법
JP2005236018A (ja) * 2004-02-19 2005-09-02 Alps Electric Co Ltd 微細配線構造および微細配線構造の製造方法
JP4559757B2 (ja) 2004-03-18 2010-10-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4769022B2 (ja) * 2005-06-07 2011-09-07 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP2007194476A (ja) 2006-01-20 2007-08-02 Shinko Electric Ind Co Ltd 多層配線基板の製造方法
US20110215465A1 (en) * 2010-03-03 2011-09-08 Xilinx, Inc. Multi-chip integrated circuit
US8377792B2 (en) * 2010-04-07 2013-02-19 National Semiconductor Corporation Method of forming high capacitance semiconductor capacitors with a single lithography step
US9491866B2 (en) * 2010-07-08 2016-11-08 Lg Innotek Co., Ltd. Method for manufacturing a printed circuit board
JP2012094662A (ja) 2010-10-26 2012-05-17 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
US8722505B2 (en) * 2010-11-02 2014-05-13 National Semiconductor Corporation Semiconductor capacitor with large area plates and a small footprint that is formed with shadow masks and only two lithography steps
US8551856B2 (en) * 2011-09-22 2013-10-08 Northrop Grumman Systems Corporation Embedded capacitor and method of fabricating the same
US9012966B2 (en) * 2012-11-21 2015-04-21 Qualcomm Incorporated Capacitor using middle of line (MOL) conductive layers

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