JP2017516305A5 - - Google Patents
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- Publication number
- JP2017516305A5 JP2017516305A5 JP2016565680A JP2016565680A JP2017516305A5 JP 2017516305 A5 JP2017516305 A5 JP 2017516305A5 JP 2016565680 A JP2016565680 A JP 2016565680A JP 2016565680 A JP2016565680 A JP 2016565680A JP 2017516305 A5 JP2017516305 A5 JP 2017516305A5
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- interconnect layer
- mol
- conductive
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 23
- 238000000034 method Methods 0.000 claims 13
- 239000004065 semiconductor Substances 0.000 claims 10
- 238000004519 manufacturing process Methods 0.000 claims 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 230000009977 dual effect Effects 0.000 claims 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- 239000010937 tungsten Substances 0.000 claims 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/274,470 | 2014-05-09 | ||
| US14/274,470 US9196583B1 (en) | 2014-05-09 | 2014-05-09 | Via material selection and processing |
| PCT/US2015/024083 WO2015171223A1 (en) | 2014-05-09 | 2015-04-02 | Via material selection and processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017516305A JP2017516305A (ja) | 2017-06-15 |
| JP2017516305A5 true JP2017516305A5 (enExample) | 2018-04-26 |
Family
ID=52875811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016565680A Pending JP2017516305A (ja) | 2014-05-09 | 2015-04-02 | ビア材料選択および処理 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9196583B1 (enExample) |
| EP (1) | EP3140857A1 (enExample) |
| JP (1) | JP2017516305A (enExample) |
| CN (1) | CN107004636B (enExample) |
| WO (1) | WO2015171223A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9620454B2 (en) * | 2014-09-12 | 2017-04-11 | Qualcomm Incorporated | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods |
| US9793212B2 (en) * | 2015-04-16 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
| US11069609B2 (en) | 2017-11-03 | 2021-07-20 | Intel Corporation | Techniques for forming vias and other interconnects for integrated circuit structures |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950010858B1 (ko) * | 1992-10-20 | 1995-09-25 | 현대전자산업주식회사 | 반도체 소자의 금속콘택 형성방법 |
| JP3175705B2 (ja) * | 1998-09-18 | 2001-06-11 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
| US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
| US6261960B1 (en) | 2000-04-06 | 2001-07-17 | Advanced Micro Devices, Inc | High density contacts having rectangular cross-section for dual damascene applications |
| JP3895126B2 (ja) * | 2001-04-23 | 2007-03-22 | 株式会社東芝 | 半導体装置の製造方法 |
| KR100930336B1 (ko) * | 2002-12-27 | 2009-12-08 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 반도체 장치, ｄｒａｍ 집적 회로 장치 및 그 제조 방법 |
| US20050285269A1 (en) | 2004-06-29 | 2005-12-29 | Yang Cao | Substantially void free interconnect formation |
| US7160772B2 (en) | 2005-02-23 | 2007-01-09 | International Business Machines Corporation | Structure and method for integrating MIM capacitor in BEOL wiring levels |
| US7863188B2 (en) * | 2005-07-29 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20070218685A1 (en) | 2006-03-17 | 2007-09-20 | Swaminathan Sivakumar | Method of forming trench contacts for MOS transistors |
| US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US7602027B2 (en) * | 2006-12-29 | 2009-10-13 | Semiconductor Components Industries, L.L.C. | Semiconductor component and method of manufacture |
| US8089160B2 (en) * | 2007-12-12 | 2012-01-03 | International Business Machines Corporation | IC interconnect for high current |
| JP5554951B2 (ja) | 2008-09-11 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2010087350A (ja) * | 2008-10-01 | 2010-04-15 | Fujitsu Microelectronics Ltd | 半導体装置とその製造方法 |
| US7999320B2 (en) | 2008-12-23 | 2011-08-16 | International Business Machines Corporation | SOI radio frequency switch with enhanced signal fidelity and electrical isolation |
| US7843005B2 (en) | 2009-02-11 | 2010-11-30 | International Business Machines Corporation | SOI radio frequency switch with reduced signal distortion |
| US8133774B2 (en) | 2009-03-26 | 2012-03-13 | International Business Machines Corporation | SOI radio frequency switch with enhanced electrical isolation |
| US8796855B2 (en) * | 2012-01-13 | 2014-08-05 | Freescale Semiconductor, Inc. | Semiconductor devices with nonconductive vias |
| US9355956B2 (en) * | 2013-11-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor for semiconductor integrated circuit |
-
2014
- 2014-05-09 US US14/274,470 patent/US9196583B1/en active Active
-
2015
- 2015-04-02 WO PCT/US2015/024083 patent/WO2015171223A1/en not_active Ceased
- 2015-04-02 CN CN201580020697.1A patent/CN107004636B/zh active Active
- 2015-04-02 EP EP15716955.8A patent/EP3140857A1/en not_active Withdrawn
- 2015-04-02 JP JP2016565680A patent/JP2017516305A/ja active Pending
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