CN107004636B - 通孔材料选择和处理 - Google Patents
通孔材料选择和处理 Download PDFInfo
- Publication number
- CN107004636B CN107004636B CN201580020697.1A CN201580020697A CN107004636B CN 107004636 B CN107004636 B CN 107004636B CN 201580020697 A CN201580020697 A CN 201580020697A CN 107004636 B CN107004636 B CN 107004636B
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- China
- Prior art keywords
- interconnect layer
- conductive material
- conductive
- layer
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/274,470 US9196583B1 (en) | 2014-05-09 | 2014-05-09 | Via material selection and processing |
| US14/274,470 | 2014-05-09 | ||
| PCT/US2015/024083 WO2015171223A1 (en) | 2014-05-09 | 2015-04-02 | Via material selection and processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107004636A CN107004636A (zh) | 2017-08-01 |
| CN107004636B true CN107004636B (zh) | 2020-07-28 |
Family
ID=52875811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580020697.1A Active CN107004636B (zh) | 2014-05-09 | 2015-04-02 | 通孔材料选择和处理 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9196583B1 (enExample) |
| EP (1) | EP3140857A1 (enExample) |
| JP (1) | JP2017516305A (enExample) |
| CN (1) | CN107004636B (enExample) |
| WO (1) | WO2015171223A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9620454B2 (en) * | 2014-09-12 | 2017-04-11 | Qualcomm Incorporated | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods |
| US9793212B2 (en) | 2015-04-16 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
| US11069609B2 (en) | 2017-11-03 | 2021-07-20 | Intel Corporation | Techniques for forming vias and other interconnects for integrated circuit structures |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261960B1 (en) * | 2000-04-06 | 2001-07-17 | Advanced Micro Devices, Inc | High density contacts having rectangular cross-section for dual damascene applications |
| CN102231361A (zh) * | 2006-12-29 | 2011-11-02 | 半导体元件工业有限责任公司 | 半导体部件及其制造方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950010858B1 (ko) * | 1992-10-20 | 1995-09-25 | 현대전자산업주식회사 | 반도체 소자의 금속콘택 형성방법 |
| JP3175705B2 (ja) * | 1998-09-18 | 2001-06-11 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
| US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
| JP3895126B2 (ja) * | 2001-04-23 | 2007-03-22 | 株式会社東芝 | 半導体装置の製造方法 |
| AU2003292827A1 (en) * | 2002-12-27 | 2004-07-29 | Fujitsu Limited | Semiconductor device, dram integrated circuit device, and its manufacturing method |
| US20050285269A1 (en) | 2004-06-29 | 2005-12-29 | Yang Cao | Substantially void free interconnect formation |
| US7160772B2 (en) | 2005-02-23 | 2007-01-09 | International Business Machines Corporation | Structure and method for integrating MIM capacitor in BEOL wiring levels |
| US7863188B2 (en) * | 2005-07-29 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20070218685A1 (en) | 2006-03-17 | 2007-09-20 | Swaminathan Sivakumar | Method of forming trench contacts for MOS transistors |
| US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US8089160B2 (en) * | 2007-12-12 | 2012-01-03 | International Business Machines Corporation | IC interconnect for high current |
| JP5554951B2 (ja) | 2008-09-11 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2010087350A (ja) * | 2008-10-01 | 2010-04-15 | Fujitsu Microelectronics Ltd | 半導体装置とその製造方法 |
| US7999320B2 (en) | 2008-12-23 | 2011-08-16 | International Business Machines Corporation | SOI radio frequency switch with enhanced signal fidelity and electrical isolation |
| US7843005B2 (en) | 2009-02-11 | 2010-11-30 | International Business Machines Corporation | SOI radio frequency switch with reduced signal distortion |
| US8133774B2 (en) | 2009-03-26 | 2012-03-13 | International Business Machines Corporation | SOI radio frequency switch with enhanced electrical isolation |
| US8796855B2 (en) * | 2012-01-13 | 2014-08-05 | Freescale Semiconductor, Inc. | Semiconductor devices with nonconductive vias |
| US9355956B2 (en) * | 2013-11-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor for semiconductor integrated circuit |
-
2014
- 2014-05-09 US US14/274,470 patent/US9196583B1/en active Active
-
2015
- 2015-04-02 JP JP2016565680A patent/JP2017516305A/ja active Pending
- 2015-04-02 CN CN201580020697.1A patent/CN107004636B/zh active Active
- 2015-04-02 EP EP15716955.8A patent/EP3140857A1/en not_active Withdrawn
- 2015-04-02 WO PCT/US2015/024083 patent/WO2015171223A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261960B1 (en) * | 2000-04-06 | 2001-07-17 | Advanced Micro Devices, Inc | High density contacts having rectangular cross-section for dual damascene applications |
| CN102231361A (zh) * | 2006-12-29 | 2011-11-02 | 半导体元件工业有限责任公司 | 半导体部件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150325515A1 (en) | 2015-11-12 |
| JP2017516305A (ja) | 2017-06-15 |
| WO2015171223A1 (en) | 2015-11-12 |
| US9196583B1 (en) | 2015-11-24 |
| EP3140857A1 (en) | 2017-03-15 |
| CN107004636A (zh) | 2017-08-01 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |